The Kernel's Write: Application Read-Only Memory

Hui Sub Shim; Katherine Mohr; Philip Levis

arxiv: 2606.26138 · v1 · pith:5HAEJ4JWnew · submitted 2026-06-18 · 💻 cs.AR · cs.OS

The Kernel's Write: Application Read-Only Memory

Hui Sub Shim , Katherine Mohr , Philip Levis This is my paper

Pith reviewed 2026-06-26 14:55 UTC · model grok-4.3

classification 💻 cs.AR cs.OS

keywords Application Read-Only MemoryLtRAMcopy-on-writememory managementDIMM hardwarepage migrationread-mostly workloadsOS kernel

0 comments

The pith

AROM lets the OS manage LtRAM by enforcing application read-only pages through copy-on-write faults, simplifying DIMM hardware while matching DRAM performance on read-mostly workloads.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper proposes Application Read-Only Memory (AROM) as a new hardware/software interface for Long-term RAM technologies that suffer from asymmetric latencies, limited endurance, and coarse write granularity. Under AROM, LtRAM pages remain read-only to applications and are written only by the operating system during page migrations, with application writes triggering CoW faults that move the page to DRAM first. This invariant shifts wear-leveling, remapping, and caching responsibilities from the on-DIMM controller to the OS, allowing simpler hardware. A sympathetic reader would care because the approach targets the plateau in DRAM cost-per-bit by delivering LtRAM's density and cost benefits without the added latency of prior translation layers.

Core claim

The central claim is that enforcing AROM via copy-on-write lets LtRAM management move from the DIMM controller to the OS, which drastically simplifies the hardware while matching pure DRAM performance on read-mostly workloads.

What carries the argument

Application Read-Only Memory (AROM): LtRAM pages that are read-only to applications and written only by the OS during migrations, enforced by CoW faults that redirect writes to DRAM.

If this is right

LtRAM DIMMs can omit on-controller translation layers for wear-leveling and caching.
OS page migration becomes the only path for writes to LtRAM.
Read-mostly applications see no performance loss compared with pure DRAM.
LtRAM density and cost advantages become available without hardware-managed read/write asymmetry penalties.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

Datacenters facing DRAM scaling limits could adopt denser LtRAM more readily if OS migration overhead stays low.
Workloads with frequent writes would likely need hybrid DRAM-LtRAM allocation policies to avoid migration storms.
The same CoW offloading pattern might extend to other asymmetric memories beyond LtRAM.

Load-bearing premise

Application writes can be efficiently redirected via CoW faults and page migrations to DRAM without introducing unacceptable latency or complexity, and workloads are read-mostly enough to benefit.

What would settle it

A workload trace or benchmark where the total latency from CoW faults and DRAM migrations exceeds the savings from simpler LtRAM hardware and lower density cost.

Figures

Figures reproduced from arXiv: 2606.26138 by Hui Sub Shim, Katherine Mohr, Philip Levis.

**Figure 1.** Figure 1: Optane internals, with a sample read path. Worstcase reads traverse the read buffer, AIT cache, and mediaresident AIT before fetching data from the 3D-XPoint media. Numbers are approximate based on prior work [14, 21]. 3.2 Case Study: Intel Optane Intel Optane, the only LtRAM-class memory ever available as a DIMM, illustrates what goes wrong when non-DRAM memory is hidden behind a DRAM interface. Each of… view at source ↗

**Figure 2.** Figure 2: DRAM to LtRAM Migration. LtRAM is a distinct memory zone with its own free list. Pages exceeding a writerecency threshold are migrated from DRAM to LtRAM via Linux’s existing page management. al. [6] measure that Optane’s aggregate sequential bandwidth collapses from ∼30 GB/s on pure reads to ∼10 GB/s under a 50/50 mixed workload, a 67% loss in read throughput. 4 Proposed Hardware/Software Interface Optan… view at source ↗

**Figure 3.** Figure 3: The Enzian research platform [1] with the NOR flash device attached. Photo from the Enzian project. 5.1 Controller The FPGA-based memory controller implements the three responsibilities specified in §4.1. The 4 KB write granularity coincides with both the OS base page size and the NOR device’s erase block size, eliminating controller-side merging. Beyond exposing the interface, the controller adds two opti… view at source ↗

**Figure 4.** Figure 4: Projected read latency through proposed interface on a DDR-class interconnect, decomposed into interconnect, on-device controller, and media access. DRAM (80–120 ns) and Optane (305–374 ns) bands serve as reference points. fast path already handles fault-on-write semantics; we extend the trigger so LtRAM-resident pages are marked CoW by default and write faults migrate the contents to DRAM before modifica… view at source ↗

read the original abstract

Alongside power, DRAM has become a major limiting factor in datacenter growth. As DRAM's cost-per-bit has plateaued over the past decade, a class of emerging memory technologies, called Long-term RAM (LtRAM), offers a path to denser and cheaper main memory. However, LtRAM has three main drawbacks: asymmetric read/write latencies, limited endurance, and coarse write granularity. In an attempt to isolate software from these drawbacks, LtRAM technologies such as Intel Optane copy an approach from flash devices and introduce a translation layer that manages wear-leveling, address remapping, and read/write caching. Prior experimental studies have found these operations add significantly to LtRAM latency. Rather than making LtRAM look like DRAM, we propose redesigning the hardware/software interface to offload more responsibility to the operating system. This design hinges on one central property, Application Read-Only Memory (AROM): LtRAM pages are read-only to applications and written only by the OS during page migrations. AROM is enforced by leveraging copy-on-write (CoW): application writes to LtRAM trigger a fault that migrates the page back to DRAM before the store is applied. This invariant allows us to shift LtRAM management from the on-DIMM controller to the operating system, drastically simplifying the DIMM's hardware. With this approach, we aim to match the performance of pure DRAM on read-mostly workloads while delivering LtRAM's density and cost advantages.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

AROM is a clean interface idea that moves LtRAM management to the OS via CoW, but the performance equivalence claim has no data or model behind it.

read the letter

AROM is a clean interface idea that moves LtRAM management to the OS via CoW, but the performance equivalence claim has no data or model behind it.

The paper introduces Application Read-Only Memory as a hardware/software contract: LtRAM pages stay read-only to applications, and any write triggers a kernel fault that migrates the page to DRAM before the store completes. This lets the DIMM drop the translation layer, wear-leveling, and caching logic that prior designs put in hardware. The abstract does a clear job showing why those on-DIMM operations add latency and why shifting the work to the OS is worth considering.

The AROM concept itself looks new relative to the translation-layer work the paper cites. The reasoning is straightforward and avoids overclaiming in the proposal.

The main gap is exactly the one the stress-test note flags. There are no latency numbers, no migration cost bounds, no write-ratio thresholds, and no workload characterization. The claim that the design matches pure DRAM on read-mostly workloads rests entirely on the untested assumption that CoW faults and page moves stay cheap. Without even a simple model, it is impossible to judge whether the hardware simplification is realistic.

This is the kind of paper that belongs in a systems reading group. It raises a legitimate question about where to draw the hardware/software line for denser memory. It shows clear thinking about the problem and the literature, so it deserves peer review even though it is still at the design-proposal stage.

Referee Report

2 major / 0 minor

Summary. The paper proposes Application Read-Only Memory (AROM) as a new hardware/software interface for Long-term RAM (LtRAM). Under AROM, LtRAM pages are read-only to applications and written only by the OS via copy-on-write faults that trigger page migrations to DRAM; this invariant is intended to allow the OS to assume responsibility for wear-leveling, remapping, and caching, thereby simplifying DIMM hardware while targeting performance parity with pure DRAM on read-mostly workloads.

Significance. If the central performance claim holds, the design would offer a concrete route to denser, lower-cost main memory by removing on-DIMM translation layers whose overhead has been documented in prior LtRAM studies. The approach is distinctive in its explicit use of CoW to enforce a read-only invariant at the application level rather than hiding LtRAM properties behind a hardware controller.

major comments (2)

[Abstract] Abstract: the claim that the design will 'match the performance of pure DRAM on read-mostly workloads' is presented without any latency model, migration-cost bound, or write-ratio threshold; the equivalence therefore remains an assertion rather than a derived result.
[Abstract] Abstract: the central design invariant (every application write routes through a kernel fault, page migration, and DRAM store) is load-bearing for both the hardware-simplification and performance claims, yet no section supplies an analytical or empirical bound on the added latency of this path relative to native DRAM writes.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the detailed and constructive feedback. We agree that the abstract makes performance claims without the necessary supporting analysis and will revise the manuscript to address this. Point-by-point responses follow.

read point-by-point responses

Referee: [Abstract] Abstract: the claim that the design will 'match the performance of pure DRAM on read-mostly workloads' is presented without any latency model, migration-cost bound, or write-ratio threshold; the equivalence therefore remains an assertion rather than a derived result.

Authors: We agree the performance goal is stated without quantitative support. Although the abstract uses 'aim to match' (rather than a definitive claim), no model or threshold is supplied. In revision we will qualify the statement to 'approach performance parity on workloads with write ratios below X%' and add a short paragraph deriving an approximate threshold from standard CoW fault costs. revision: yes
Referee: [Abstract] Abstract: the central design invariant (every application write routes through a kernel fault, page migration, and DRAM store) is load-bearing for both the hardware-simplification and performance claims, yet no section supplies an analytical or empirical bound on the added latency of this path relative to native DRAM writes.

Authors: This is correct; the manuscript provides no bound on CoW-plus-migration latency. The design's viability rests on this path being rare, yet the overhead is unquantified. We will insert an analytical estimate (drawing on published page-fault and migration latencies) into the introduction or a new short section, together with a discussion of its effect on the read-mostly target. revision: yes

Circularity Check

0 steps flagged

Conceptual redesign proposal exhibits no circularity

full rationale

The paper is a hardware/software interface redesign proposal centered on the AROM invariant enforced by CoW faults and OS page migrations. No equations, fitted parameters, derivations, or mathematical claims appear in the provided text. Central assertions (performance equivalence on read-mostly workloads, hardware simplification) are presented as design goals rather than results derived from prior inputs or self-citations. No load-bearing steps reduce by construction to the paper's own definitions or fitted values. This is a normal non-finding for a conceptual architecture paper.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 1 invented entities

Abstract-only review; no free parameters, axioms, or invented entities beyond the core AROM concept are detailed. The proposal rests on unstated assumptions about workload characteristics and migration costs.

invented entities (1)

Application Read-Only Memory (AROM) no independent evidence
purpose: Enforce read-only access for applications on LtRAM pages with OS-only writes during migrations
Central new concept introduced to simplify hardware; no independent evidence provided.

pith-pipeline@v0.9.1-grok · 5789 in / 1058 out tokens · 20068 ms · 2026-06-26T14:55:57.128509+00:00 · methodology

discussion (0)

Reference graph

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Huaicheng Li, Daniel S. Berger, Lisa Hsu, Daniel Ernst, Pantea Zar- doshti, Stanko Novakovic, Monish Shah, Samir Rajadnya, Scott Lee, Ishwar Agarwal, Mark D. Hill, Marcus Fontoura, and Ricardo Bian- chini. 2023. Pond: CXL-Based Memory Pooling Systems for Cloud Platforms. InProceedings of the 28th ACM International Conference on Architectural Support for P...

work page doi:10.1145/3575693.3578835 2023

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work page doi:10.1145/3764862.3768175 2025

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