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arxiv: 2607.06456 · v1 · pith:6DVK6ISY · submitted 2026-07-07 · eess.SP · cs.NE

A Hardware-Aware Open-Source Framework for Design Space Exploration of Mixed-Signal Spiking Neural Networks

Sayma Nowshin Chowdhury , Vineeta Nair , Taseen Forhad , Aishwarya Natarajan , Corey Hart , Sahil Shah This is my paper

Reviewed by Pith T0 review T1 audit T2 compute T3 formal T4 reserved 2026-07-08 05:08 UTCglm-5.2pith:6DVK6ISYrecord.jsonopen to challenge →

Figure 1
Figure 1. Figure 1: Impact of hardware non-idealities on neuromorphic learning and inference: [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] reproduced from arXiv: 2607.06456
classification eess.SP cs.NE PACS 84.30.Sk85.40.-e
keywords frameworkdesignexplorationmixed-signalspikingaccuracyareaenables
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The pith

Train spiking nets on physical device parameters, not abstract weights

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents an open-source simulation framework that embeds experimentally calibrated, nonlinear device physics from floating-gate (FG) transistors and ReRAM devices directly into a PyTorch-based spiking neural network (SNN) training loop. Instead of training on idealized abstract weights and then mapping them onto analog hardware afterward—a process that typically degrades accuracy by 8–11%—the framework makes the trainable parameters themselves physical quantities: floating-gate voltage (V_FG0) for FG synapses and filament gap (g) for ReRAM synapses. The neuron models (Axon-Hillock, adaptive LIF, Schmitt-trigger LIF, Hodgkin-Huxley) are likewise parameterized by circuit-level quantities and validated against transistor-level Cadence simulations in 65 nm and 28 nm CMOS. The result is a tool that can jointly report classification accuracy, silicon area, power consumption, and quantization sensitivity across neuron-synapse-architecture combinations on standard neuromorphic benchmarks (N-MNIST, DVS Gesture, SHD), enabling systematic design-space exploration before fabrication.

Core claim

The central contribution is the demonstration that nonlinear analog device models can be made differentiable and embedded as custom PyTorch modules, so that backpropagation-through-time (BPTT) with surrogate gradients directly optimizes physical synaptic parameters rather than abstract weights. This eliminates the post-training weight-mapping step that introduces accuracy loss when software-trained SNNs are deployed on mixed-signal hardware. The framework validates this approach by showing close agreement between Python-based simulation and Cadence transistor-level simulation on an XOR task (matching area to 0.003543 mm² and power to 24.958 µW), and then extends it to three benchmarkdatasets

What carries the argument

The mechanism is a chain rule decomposition: the synaptic weight W_ij is treated as a function f(theta_ij) of a physical device parameter theta (V_FG0 or filament gap g), so the training gradient flows as dL/dtheta = (dL/dW) * (dW/dtheta), with dW/dtheta computed from the nonlinear device I-V model embedded as a custom differentiable PyTorch module. Surrogate gradients handle the non-differentiable spike threshold. Post-training quantization (8-bit for FG, 3-bit for ReRAM) then projects continuous trained parameters onto physically realizable discrete levels.

If this is right

  • Eliminating post-training weight mapping could reduce the calibration engineering effort currently required to deploy SNNs on analog neuromorphic chips, potentially making mixed-signal neuromorphic systems more accessible to algorithm researchers.
  • The framework's modular design allows systematic comparison of neuron-synapse combinations: for example, ReRAM synapses reduce area by over 100x compared to FG synapses but with measurable accuracy trade-offs, giving chip designers concrete Pareto frontiers.
  • The tool's ability to report area and power alongside accuracy for arbitrary architectures enables hardware-aware neural architecture search, where the objective function could incorporate physical constraints directly.
  • If the mean-behavior device models are sufficiently predictive, the framework could serve as a pre-fabrication screening tool, letting designers identify promising neuron-synapse-architecture configurations before committing to expensive silicon fabrication runs.

Load-bearing premise

The framework models only the mean behavior of synapse and neuron devices, explicitly omitting device-to-device and cycle-to-cycle variability, transistor mismatch, parasitic capacitances, and temporal drift. If these stochastic variations dominate network-level performance in fabricated silicon, the deterministic predictions of the tool will diverge from real hardware behavior.

What would settle it

Fabricate a mixed-signal SNN chip using one of the neuron-synapse configurations explored by the framework, then compare on-chip classification accuracy, area, and power against the tool's predictions. If device mismatch and cycle-to-cycle ReRAM variability cause accuracy to drop substantially below the framework's mean-behavior prediction (e.g., by more than the 8-11% degradation already observed for nonlinearity alone), the tool's utility as a predictive design instrument is undermined.

Figures

Figures reproduced from arXiv: 2607.06456 by Aishwarya Natarajan, Corey Hart, Sahil Shah, Sayma Nowshin Chowdhury, Taseen Forhad, Vineeta Nair.

Figure 2
Figure 2. Figure 2: General flow of the proposed simulation framework for mixed-signal SNNs. [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Dynamics of representative spiking neuron models: Input spikes are [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: The figure shows the current vs input voltage relationships of an FG [PITH_FULL_IMAGE:figures/full_fig_p008_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Figure illustrating the python code for defining a custom pytorch class and [PITH_FULL_IMAGE:figures/full_fig_p009_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Current-voltage (I-V) characteristics of the ReRAM device. The ReRAM [PITH_FULL_IMAGE:figures/full_fig_p011_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: A demonstration of Python code that defines a custom PyTorch class and [PITH_FULL_IMAGE:figures/full_fig_p012_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: (a) Axon hillock circuit (b) LIF neuron circuit [PITH_FULL_IMAGE:figures/full_fig_p013_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Comparison of ISI vs. synaptic current between the Python model and [PITH_FULL_IMAGE:figures/full_fig_p015_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: (a) Hodgkin-Huxley neuron model (b) ISI vs. synaptic current for HH [PITH_FULL_IMAGE:figures/full_fig_p016_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: (a) Fully connected architecture (b) Recurrent connected architecture [PITH_FULL_IMAGE:figures/full_fig_p017_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Visualization of DVS Gesture dataset events spatial downsampling from [PITH_FULL_IMAGE:figures/full_fig_p020_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: XOR Logic Decoding using Spiking Neural Activity in 65 nm [PITH_FULL_IMAGE:figures/full_fig_p021_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: FG synapse-based SNN architecture for SHD dataset classification. (a) [PITH_FULL_IMAGE:figures/full_fig_p023_14.png] view at source ↗
read the original abstract

Energy-efficient neuromorphic computing at the edge requires simulation tools that can capture the non-ideal behavior of mixed-signal spiking neural network (SNN) hardware while supporting system-level design exploration. This work presents an open-source hardware-aware simulation framework for mixed-signal SNNs that enables comparative analysis across neuron, synapse and architecture choices. The framework supports multiple neuron models, including Leaky Integrate-and-Fire (LIF), Hodgkin-Huxley (HH) and Axon-Hillock (AH), together with non-volatile analog synapses based on floating-gate transistors and ReRAM devices. By incorporating device-level nonlinearities directly into PyTorch-based training and inference, the tool enables optimization of physical synaptic parameters rather than idealized abstract weights. The framework is evaluated on standard neuromorphic benchmarks, including N-MNIST, DVS Gesture and Spiking Heidelberg Digits (SHD). For each model dataset configuration, it reports classification accuracy together with hardware-oriented metrics such as silicon area, power consumption and quantization sensitivity. These capabilities enable cross-layer design space exploration and help identify neuron-synapse configurations that best satisfy application-specific constraints on accuracy, energy efficiency, area and hardware fidelity.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

4 major / 9 minor

Summary. This paper presents an open-source PyTorch-based simulation framework for mixed-signal spiking neural networks (SNNs) that embeds experimentally calibrated floating-gate (FG, 65nm) and ReRAM (130nm) synapse models alongside multiple mixed-signal neuron models (AH, LIF, HH, Schmitt-LIF) directly into the training loop. The framework enables optimization of physical device parameters (V_FG0, filament gap g) rather than abstract weights, and reports accuracy, area, and power across N-MNIST, DVS Gesture, and SHD benchmarks. Neuron models are validated against Cadence transistor-level simulations via ISI comparisons, and an XOR task validates the full FG-synapse + LIF-neuron pipeline against SPICE. The central contribution is the co-design tool itself, which bridges device physics and network-level learning.

Significance. The framework addresses a genuine gap between algorithmic SNN research and mixed-signal hardware deployment. Embedding calibrated device equations (Eq. 1, Eq. 3) into differentiable PyTorch modules so that gradient-based training directly updates physical parameters (V_FG0, g) is a meaningful design choice. The Cadence ISI validation (Figs. 9, 10) and XOR cross-validation (Section 6.1) provide concrete fidelity checks. The open-source release and the systematic area/power/accuracy trade-off tables (Tables 2-4) are valuable for the neuromorphic hardware community. The paper is honest about limitations (Section 8), explicitly noting the omission of mismatch, parasitics, and AER routing.

major comments (4)
  1. Section 1 and Section 5 claim the framework 'eliminates the need for post-training weight mapping.' However, Section 3.1.1 explicitly states 'the continuous floating-point weights obtained after training must be mapped to discrete levels that are physically realizable on the FG device,' and applies 8-bit (FG) or 3-bit (ReRAM) post-training quantization. Table 4 shows this step causes 5-7% accuracy drops (e.g., N-MNIST 86.79% to 81.24% with 3-bit ReRAM). The training loop (Figs. 5, 7) computes continuous device currents without discretization in the forward pass. This is precisely post-training weight mapping — from continuous physical parameters to discrete device states. The claim should be narrowed from 'eliminating' to 'reducing' or 'minimizing' post-training weight mapping, or quantization-aware training should be integrated into the loop. As stated, the central claim is contradicted
  2. Section 6.1 states 'the learned weights (VFG0) were mapped onto the Verilog-A model of the FG synapse for circuit-level evaluation in Cadence.' This is an explicit post-training mapping step for the XOR validation, directly contradicting the claim of elimination. The authors should acknowledge this step and reconcile it with the framing in Section 1.
  3. Table 2 reports accuracy drops of 8-11% (N-MNIST) and 7-8% (DVS Gesture) when replacing ideal synapses with hardware-aware models. The paper does not perform an ablation to separate the contributions of synapse nonlinearity, neuron model differences, and training instability. Section 7 acknowledges this ('disentangling the individual contribution of each factor through a dedicated ablation study remains an important direction for future work'), but without any decomposition, it is unclear whether the accuracy gaps reflect fundamental device physics limitations or suboptimal training. A simple ablation (e.g., ideal synapse + AH neuron vs. ReRAM synapse + ideal neuron) would strengthen the design-space exploration claims.
  4. Section 8 states the framework 'does not include... mismatch effects, parasitics and temporal drift.' The device models capture mean behavior only (Section 3.1.2: 'the device model is designed to capture the mean device behavior'). For a predictive design tool, the absence of device-to-device and cycle-to-cycle variability is a significant scope limitation, since these effects often dominate network-level accuracy in fabricated mixed-signal SNNs. The paper should more prominently qualify that the reported accuracy, area, and power predictions are best-case bounds, not expected silicon performance.
minor comments (9)
  1. Table 3 caption mentions 'Adaptive LIF neurons' but the N-MNIST ReRAM row in Table 2 uses 'LIF(65 nm)' and 'Sch-LIF (28 nm)'. Clarify which neuron model corresponds to the Table 3 ReRAM entry.
  2. Table 4 DVS Gesture row: the synapse type is missing. It should specify ReRAM or FG to match the other rows.
  3. Figure 5 and Figure 7 show code snippets with truncated variable names (e.g., 'Fg_current_weights_pre', 'w_fil_p'). These are difficult to read. Consider using cleaner pseudocode or larger font.
  4. Section 3.2.1, Eq. (6): the surrogate gradient function is denoted Θ in the equation but σ(·) in Section 3.2.2, Eq. (9). Use consistent notation.
  5. Section 6.2: 'the digital baseline achieves a test accuracy of 95.20%' for N-MNIST, but Table 2 lists 95.20% test accuracy for nn.Linear + snn.Leaky. The DVS Gesture digital baseline (81.06%) is notably low compared to published results on this dataset. A brief discussion of why the baseline accuracy is modest would help contextualize the hardware-aware results.
  6. Table 3: the 'Area' column header includes 'M' (e.g., '0.341 M'). Clarify whether this means million transistors or another unit.
  7. Section 3.1.1: the quantization range is described as V_FG0 ∈ [-0.4, +0.4] mapped to [-0.15, +0.15] in the supplementary material (Section 12.1). Explain why the representable range is narrower than the training range and how weights outside [-0.15, +0.15] are handled (clipping is mentioned but not quantified).
  8. Reference [43] (Didin et al., 2026) and [58] (Boyle et al., 2025) appear to be very recent or forthcoming. Verify these are properly cited and accessible.
  9. The abstract states 'quantization sensitivity' as a reported metric, but only Table 4 reports quantization results. Consider adding quantization sensitivity analysis for more configurations to substantiate this claim.

Simulated Author's Rebuttal

4 responses · 0 unresolved

We thank the referee for a careful and constructive review. The referee correctly identifies an internal contradiction in our framing of the post-training quantization step relative to the claim of 'eliminating post-training weight mapping.' We accept this point and will revise the manuscript accordingly. We also accept the call for an ablation study and for more prominent qualification of the variability omission. Below we address each comment in detail.

read point-by-point responses

  1. Referee: Sections 1 and 5 claim the framework 'eliminates the need for post-training weight mapping,' but Section 3.1.1 describes post-training quantization to discrete levels, and Table 4 shows accuracy drops from this step. The claim is contradicted.

    Authors: The referee is correct. The manuscript as written contains an internal contradiction. The training loop optimizes physical device parameters (V_FG0, g) through the nonlinear device equations, which is a genuine difference from conventional approaches that train abstract weights and then map them to a device transfer curve. However, the subsequent post-training quantization to 8-bit (FG) or 3-bit (ReRAM) discrete levels is itself a form of post-training weight mapping, and our claim of 'eliminating' it is overstated. We will revise the language in Sections 1 and 5 from 'eliminating' to 'reducing' or 'minimizing' the gap between trained parameters and hardware-realizable states, and we will explicitly acknowledge the quantization step as a remaining post-training mapping operation. We will also note in the revised text that integrating quantization-aware training into the loop is a natural extension that would further reduce this remaining gap. revision: yes

  2. Referee: Section 6.1 states learned weights (VFG0) were mapped onto the Verilog-A model for Cadence evaluation, which is an explicit post-training mapping step contradicting the claim of elimination.

    Authors: We agree. The XOR validation in Section 6.1 involves transferring trained V_FG0 values to a Verilog-A model for circuit-level simulation, which is indeed a post-training mapping step. This does not contradict the revised framing we will adopt per the previous comment, but it does contradict the original 'elimination' claim. We will revise Section 6.1 to explicitly acknowledge this mapping step and reconcile it with the corrected framing in Sections 1 and 5. The value of the XOR validation is as a fidelity cross-check between the Python model and SPICE-level simulation, not as evidence that mapping is unnecessary. revision: yes

  3. Referee: Table 2 shows 8-11% accuracy drops from hardware non-idealities, but no ablation separates synapse nonlinearity, neuron model differences, and training instability. Section 7 acknowledges this as future work.

    Authors: We agree that an ablation study would strengthen the paper and clarify whether the accuracy gaps reflect fundamental device limitations or suboptimal training. We will conduct and include a limited ablation in the revised manuscript, specifically: (1) ideal synapse + hardware neuron model (e.g., nn.Linear + AH/LIF), and (2) hardware synapse + ideal neuron (e.g., ReRAM + snn.Leaky). This will decompose the accuracy loss into synapse-attributable and neuron-attributable components. We note that fully disentangling training instability from device nonlinearity would require additional experiments with alternative learning rates and training schedules, which we will discuss but may not fully execute within the revision timeline. We will update Section 7 accordingly. revision: partial

  4. Referee: Section 8 omits mismatch, parasitics, and drift. Device models capture mean behavior only. For a predictive design tool, absence of variability is a significant scope limitation. Reported metrics should be qualified as best-case bounds.

    Authors: We agree that the absence of device-to-device and cycle-to-cycle variability is a significant scope limitation and that the reported accuracy, area, and power numbers should be explicitly qualified as best-case (or nominal-case) bounds rather than expected silicon performance. We will add a prominent qualification to this effect in Section 8 and also reference it in the abstract and Section 6.2 where the metrics are reported. We note that integrating variability models is a substantial modeling effort that goes beyond the scope of the current revision, but we will make the limitation unambiguous to any reader using the tool for design decisions. revision: yes

Circularity Check

0 steps flagged

No significant circularity; self-citations provide experimental calibration data, not theoretical assertions that reduce to the paper's own conclusions.

full rationale

The paper's core derivation chain is not circular. The device models (Eq. 1 for FG synapses, Eq. 3 for ReRAM) are calibrated against experimental data from fabricated chips (65nm FG, 130nm ReRAM), with fitted parameters extracted from measured I-V characteristics (Figs. 4, 6). The training methodology (Eqs. 12-15) embeds these calibrated device equations into standard BPTT with surrogate gradients — a standard chain-rule formulation with no self-referential dependency. The accuracy, area, and power predictions (Tables 2-4) are computed from these independently grounded models and from Cadence-extracted component metrics, not fitted to the target benchmark results. Several self-citations exist (refs [37], [43], [47], [59] share author Shah), but these provide experimental characterization data — measured conductance ranges, voltage levels, and circuit parameters — that are externally falsifiable measurements from fabricated devices, not theoretical claims whose validity depends on the present paper's conclusions. The quantization schemes (Supplementary Sec. 12) are grounded in measured device characteristics from these prior works. The XOR validation (Sec. 6.1) cross-checks Python predictions against independent Cadence transistor-level simulations. The skeptic's concern about the 'eliminating post-training weight mapping' claim being contradicted by the actual post-training quantization step is a correctness/consistency issue, not a circularity issue — the quantization does not make any prediction equivalent to its input by construction. Score 2 reflects minor self-citation for calibration data that is not load-bearing for circularity.

Axiom & Free-Parameter Ledger

3 free parameters · 4 axioms · 0 invented entities

The ledger captures the fitted device parameters and the core domain assumptions. No new physical entities or particles are invented; the models are grounded in existing CMOS devices and standard neuron equations.

free parameters (3)
  • FG device parameters (κ, UT, σ, Ithpmos, CT, etc.) = Extracted from 65nm measurements
    Parameters for the EKV-based FG synapse model (Eq. 1) are fitted to experimental I-V data from fabricated devices.
  • ReRAM calibration parameters (I0, g0, V0) = Extracted from 130nm measurements
    Parameters for the ReRAM I-V model (Eq. 3) are derived from physical device measurements.
  • Neuron circuit parameters (Cmem, Vth, leak currents, etc.) = Extracted from Cadence simulations
    Parameters for AH, LIF, and HH neuron models are matched to transistor-level Cadence simulations in 65nm and 28nm nodes.
axioms (4)
  • domain assumption Mean device behavior is sufficient to model network-level performance.
    The framework models mean device behavior and explicitly omits device-to-device and cycle-to-cycle variability (Section 3.1.2, Section 8).
  • domain assumption First-order Euler integration is sufficient for simulating neuron dynamics.
    The paper uses simple forward Euler update for discretizing membrane potential dynamics (Eq. 5, Eq. 8).
  • standard math Surrogate gradient methods effectively approximate the non-differentiable spike generation function for BPTT.
    The framework adopts standard surrogate gradient methods to handle the non-differentiable spike function (Section 5).
  • domain assumption Point neuron models capture the essential dynamics for the target applications.
    The framework is based on point neuron models, omitting complex dendritic or compartmental dynamics (Section 7).

pith-pipeline@v1.1.0-glm · 23295 in / 2524 out tokens · 431449 ms · 2026-07-08T05:08:17.029959+00:00 · methodology

discussion (0)

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