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All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices

T0 review · 4 major / 6 minor · reviewed 2026-08-08 · deepseek-v4-flash

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Pith's one-line read A single CMO/HfO$_x$ ReRAM array can train neural networks on-chip and then retain weights for long-term inference, with matrix-vector-multiplication error lower by a factor of 20 at one second and 3 at ten years than prior analog memory.

desk verdict Solid device characterization wrapped in an overclaiming all-in-one narrative: training is simulated, not measured, and prior art is mischaracterized. read the letter →

arxiv 2502.04524 v4 pith:2WRRCVEI submitted 2025-02-06 cs.ET cs.AR

Donato Francesco Falcone , Victoria Clerico , Wooseok Choi , Tommaso Stecconi , Folkert Horst , Laura Begon-Lours , Matteo Galetta , Antonio La Porta
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Nikhil Garg Fabien Alibart Bert Jan Offrein Valeria Bragaglia
This is my paper · ORCID
classification cs.ETcs.AR
keywords in-memorycomputinganalogReRAMCMO/HfOxon-chiptraininginferenceaccelerationconductancerelaxationweighttransfer1T1Rarray
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that a single memory technology can cover the whole analog-AI pipeline — on-chip training, weight retention, and long-term inference — on the same chip, something no previously reported platform has done. The devices are conductive-metal-oxide/HfO$_x$ resistive memory cells arranged as one-transistor-one-resistor units in the back-end-of-line of a 130 nm CMOS process, switching below 1.5 V and programmable into more than 32 distinguishable conductance states with programming noise between 10 and 100 nS. Hardware-aware simulations of a $64\times 64$ tile project a matrix-vector-multiplication root-mean-square error of 0.03 one second after programming and 0.2 after ten years, which the authors report as improvements by a factor of 20 and 3 over a published ReRAM compute-in-memory chip. The same array, driven by identical open-loop pulses, shows gradual bidirectional conductance updates, and hardware-aware simulations of the AGAD algorithm built on those measured statistics reach 96.9% accuracy on MNIST against a 98.3% floating-point baseline, with comparable perplexity on an LSTM text task. If these results hold, an autonomous AI system could train itself on the chip and then keep running inference for years without separate digital training hardware.

What carries the argument

The central object is the conductive-metal-oxide layer inserted between the top electrode and the HfO$_x$ switching layer, operated in filamentary mode so that charge transport is trap-to-trap tunneling described by a Mott-Gurney hopping model. The CMO layer confines the electric field and temperature at the filament tip, so resistive switching proceeds by radial redistribution of oxygen vacancies in a defect sub-band of the CMO, yielding the gradual bidirectional conductance updates that training needs. Two further choices carry the argument: re-optimizing the switching polarity from counter-eightwise to eightwise so the NMOS selector in each one-transistor-one-resistor cell can control the fast set transition, and an identical-pulse closed-loop programming scheme whose measured noise-versus-iteration trade-off feeds the inference simulations. The ten-year projection itself rests on a measured relaxation law — after programming, the mean of a conductance state drifts down and its standard deviation grows, both approximately linearly with the logarithm of elapsed time and nearly independent of the programmed value — extrapolated from one week of data, and on a hardware-aware simulation stack that folds in programming noise, relaxation, 6-bit/8-bit input/output quantization, and IR drop.

What would settle it

Age the same programmed 50 $\mu$S states for several additional months, and in parallel at elevated temperature such as 85 °C mapped back to room temperature, then test whether the mean drift and standard-deviation growth still lie on the log-time lines that produced the ten-year distributions. As a separate check, rerun the paper's $64\times 64$ matrix-vector protocol with the reference chip's published device and drift parameters under identical 6-bit/8-bit quantization and readout conditions; if the reference RMSE under those conditions comes out materially below the 0.58 the paper uses as its baseline, the reported improvement factors would shrink by the same proportion.

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Extended reading notes

Core claim

On the paper's own terms, the finding is that the engineered conductive-metal-oxide layer in an otherwise conventional HfO$_x$ ReRAM stack produces a cell that satisfies the conflicting requirements of analog training and analog inference in the same array. For inference, closed-loop programming with fixed-amplitude pulses yields an almost ideal weight transfer — programming noise of 10 to 100 nS across a 10 to 90 $\mu$S window, more than 32 stable states, and less than 10% overlap between adjacent state distributions after 10 minutes — and a relaxation process whose mean shift and distribution width grow linearly with log time and are nearly independent of the programmed conductance, which is what allows the ten-year accuracy projection. For training, the same cells respond to an open-loop identical-pulse scheme with gradual, bidirectional conductance changes across the whole array, averaging 22 states, a 61% symmetry-point skew toward depression, and a 90% noise-to-signal ratio at the symmetry point. Simulated AGAD training on these measured statistics reaches 96.9% test accuracy on MNIST against a 98.3% floating-point baseline, and near-baseline perplexity on a two-layer LSTM next-token task, which the paper takes as evidence that the platform scales from fully connected networks to sequence models. The unifying claim is that one one-transistor-one-resistor array, integrated in the back-end-of-line of a standard CMOS process with switching below 1.5 V, carries both capabilities, making a continuously retraining analog AI core physically plausible.

Load-bearing premise

The load-bearing premise is that conductance relaxation measured for one week, with the mean and standard deviation fitted as linear functions of the logarithm of elapsed time, keeps following those same lines for ten years; if the drift slows, accelerates, or becomes dependent on the programmed state on longer timescales, the projected ten-year matrix-vector accuracy and the claimed factor-of-3 advantage lose their support.

Editorial extensions

If this is right

  • If the ten-year relaxation extrapolation holds, a programmed CMO/HfO$_x$ tile can serve untended for roughly a decade: the simulated $64\times 64$ matrix-vector RMSE stays at 0.2 without refresh, re-programming, or digital compensation.
  • At short timescales the dominant matrix-vector error is input/output quantization (6-bit/8-bit), not the devices, so higher-resolution converters attached to the same array would push inference accuracy well below the reported RMSE.
  • On-chip training with the AGAD algorithm on the measured device statistics reaches 96.9% on MNIST, within 1.4 points of floating point, and near-baseline LSTM perplexity, so the same core is a credible training accelerator rather than an inference-only memory.
  • Because the technology is back-end-of-line integrated in a standard 130 nm CMOS process with sub-1.5 V switching, the all-in-one core can sit alongside conventional digital logic, and in larger $512\times 512$ tiles the accuracy bottleneck shifts to IR drop on the wires rather than device non-idealities.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper's own numbers allow a near-free compensation scheme that it does not explicitly propose: since the mean relaxation drift is about $-0.7$ $\mu$S and nearly state-independent, a single per-tile bias or a fixed post-programming wait-and-measure step could cancel most of the projected drift.
  • The log-time relaxation law is the long pole of the whole project; accelerated aging at elevated temperature (the paper cites under 4% drift after 72 hours at 85 °C for a similar stack) could validate or refute the ten-year projection in weeks rather than a decade.
  • The paper leaves open how repeated open-loop weight updates during on-chip retraining perturb already-programmed neighboring cells in a larger tile; if that disturbance is small, the training and inference demonstrations merge into a single continuous learning loop, which is the implicit end-goal of the all-in-one concept.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. The paper reports an 8x4 BEOL-integrated CMO/HfOx ReRAM array in a 1T1R configuration and uses it to support claims of an 'all-in-one' analog AI platform for both on-chip training and long-term inference. Measured results include forming statistics, quasi-static switching with 8W polarity, 35 programmable conductance levels, low programming noise, one-week conductance relaxation data, and open-loop pulse-response statistics. System-level claims are obtained by hardware-aware simulations in IBM's aihwkit: 64x64 MVM accuracy projections up to 10 years after programming, and MNIST/LSTM training accuracy using the AGAD algorithm. The paper positions these simulations as evidence that the same array can support both training and inference acceleration.

Significance. If the central claims were fully supported, the work would be a valuable device-platform demonstration: low programming noise (sub-0.1 uS), 32+ distinguishable states, BEOL integration in a 1T1R array, and open-loop response statistics are useful for the analog in-memory computing community. The explicit reporting of fitted model parameters and code availability are strengths. However, the headline system-level contributions are model extrapolations rather than measured array-level results, so the significance as an 'all-in-one accelerator demonstration' is currently prospective rather than demonstrated.

major comments (4)
  1. [Abstract; Section 2.3.2; Methods 4.7] The claim of demonstrated on-chip training is not supported by hardware measurements. The MNIST and LSTM results in Fig. 6 are produced by aihwkit simulations using the generalized soft bounds model fitted to the 32-device open-loop pulse responses of Fig. 5; Methods 4.7 explicitly states 'HW-aware simulation of analog training.' No training loop was executed on the 8x4 array. The abstract's statement that 'training accuracy closely matching the software equivalent is achieved' presents a simulation projection as an experimental achievement. Please either add measured array-level training results or reframe the abstract, Section 1, and Table 1 so that the training pillar is described as a hardware-calibrated simulation, not a demonstration.
  2. [Section 2.2.2; Fig. 4e; Methods 4.6.2] The 10-year MVM projection is an unsupported extrapolation. The extended relaxation characterization covers one week at a single representative conductance (50 uS), and the insets of Fig. 4e fit the mean and standard deviation as linear functions of log time. The assumption that this trend continues for 10 years is not physically justified in the manuscript, and no uncertainty band is given. Because the headline factor-of-20 and factor-of-3 improvements over Wan et al. are derived from this extrapolation, the 10-year inference claim currently rests on an unvalidated fitting assumption. Please either restrict the retention claims to the measured timescale, provide a physics-based justification with uncertainty quantification, or add longer-term experimental data.
  3. [Section 2.2.2; Fig. 4f] The comparison to Wan et al. [9] compares a simulation against an experiment. The Wan et al. RMSE of approximately 0.58 is stated to be experimentally determined, whereas the CMO/HfOx RMSE of 0.03 at 1 s and 0.2 at 10 years is generated by aihwkit with a dedicated phenomenological noise model fitted to this work's device data. The simulation conditions also differ in array size, programming scheme, and the specific quantization and IR-drop settings. This is therefore not a controlled head-to-head benchmark. Please state these differences explicitly and describe the factor-of-20/3 claims as projected, model-based improvements rather than demonstrated advantages.
  4. [Methods 4.6; Methods 4.7; Fig. 4f] The MVM and training simulations are in-sample evaluations of the same fitted device models, which limits their predictive force. The programming noise coefficients (Fig. 3e), the relaxation coefficients (Fig. 4e), and the generalized soft bounds parameters (Methods 4.7.1) are all extracted from the same measured device responses that are then used as simulation inputs. The resulting accuracy numbers therefore encode the fitted assumptions rather than independently validating the model. Please add a clear statement that the simulations are calibrated projections, and ideally validate the model on held-out devices or on an actual 64x64 array if the extrapolated claims are retained.
minor comments (6)
  1. [Section 2.2.2; Fig. 4c/4d] The claim that relaxation is independent of the programmed conductance is supported by one-hour data spread across the range and by one-week data at a single state (50 uS). Please clarify in the text that the state independence has not been verified on the one-week timescale across the full conductance window.
  2. [Section 2.3.1; Eq. (3)] The NSR definition in Eq. (3) is written as sigma_DeltaGsp / DeltaGsp, but the text reports values around 90%. Please define whether this is a percentage ratio and clarify the normalization used in the reported metric.
  3. [Methods 4.2; Eq. (4)] Equation (4) appears malformed: 'nabla . Je = nabla . (sigma(-nabla V) = 0' has a misplaced equality. It should presumably read 'nabla . (sigma(-nabla V)) = 0' or equivalent. Please correct.
  4. [General] The manuscript uses '8W' and 'C8W' switching polarity without defining the notation in the figure captions or in the text. Please add a definition, since these terms are not self-explanatory to all readers.
  5. [Table 1] The column 'Model Fidelity' is not defined by a quantitative metric. Since the table is used to benchmark the device model, please state how 'Medium' and 'High' are assessed, or provide a numerical fidelity score.
  6. [Section 2.2.2; Fig. 4f caption] The figure caption states that the simulations consider 'experimental programming noise, conductance relaxation, limited input/output quantization and IR-drop,' but the Discussion later states that read noise is not included. Please add a note in the caption and in the text to avoid ambiguity about which measured non-idealities are included.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: MVM accuracies and training results are forward simulations from experimentally extracted device parameters, not reductions of the conclusions to the inputs.

full rationale

The central quantitative claims—MVM RMSE at 1 second and 10 years, and MNIST/LSTM training accuracy—are generated by aihwkit simulations that ingest experimentally measured programming noise, conductance relaxation, and open-loop pulse response statistics. These are genuine forward computations: the fitted sigma_prog(G_target) and the linear-in-log-time mean/std relaxation laws do not by themselves contain the RMSE or accuracy numbers; those emerge from simulated matrix-vector multiplications and training runs. The 10-year RMSE is an extrapolation of a one-week relaxation fit and is therefore vulnerable to model error, but that is a correctness and validation concern, not circularity. Likewise, the training pillar is supported only by simulation, not by a hardware training loop on the 8x4 array; this is an evidentiary gap relative to the 'all-in-one on-chip training' claim, not a logical equivalence between premise and conclusion. The comparison with Wan et al. uses simulation conditions chosen by the authors, so the factor-of-20/3 improvement is a projected rather than directly measured benchmark; again, this affects strength of evidence, not circularity. Self-citations to prior CMO/HfOx device work (refs. 24-26, 31-32) provide background physics and single-device criteria, but the array-level switching, programming noise, relaxation, and open-loop responses central to this paper are measured and reported in this manuscript. No equation or fitted parameter is renamed as the predicted quantity, and no load-bearing argument reduces to a self-citation. Under the stated standard requiring an explicit Eq. X = Eq. Y reduction, no circular step is present.

Assumptions & free parameters 6 free parameters · 5 assumptions · 0 invented entities

The central system-level claims depend on several fitted models: the transport model, the programming noise fit, the relaxation extrapolation, and the soft bounds device model for training simulations. No new physical entities are introduced. The 10-year and training results are derived from these fitted models rather than from direct measurement.

free parameters (6)
  • r_CF (conductive filament radius) = 11 nm
    Extracted from fitting the forming I-V data in the low-voltage linear regime (Section 4.2, Fig. S1).
  • sigma_CMO (CMO electrical conductivity, two values) = 5 S/cm and 37 S/cm
    Used in FEM forming model; 5 S/cm for initial state, 37 S/cm after negative sweep defect redistribution (Section 4.2).
  • N_e, DeltaE_e, a_e (trap-to-trap tunneling parameters) = e.g., N_LRS=5e19 cm-3, E_LRS=65 meV, a_LRS=2.1 nm; HRS values given in Fig. 2d
    Extracted from fitting the I-V characteristics using the Mott-Gurney model (Section 4.4, Fig. 2d).
  • Programming noise model coefficients = sigma_prog = 10^-3*(1.1*G+0.8) and 10^-3*(11.3*G+11.2) for 0.2% and 2% acceptance ranges
    Linear fits to measured standard deviation vs target conductance (Fig. 3e, Section 4.6.1).
  • Conductance relaxation model coefficients = Linear fits of mean and std vs log time, measured to 1 week
    Used to project relaxation to 10 years in MVM simulations (Section 4.6.2, Fig. 4e).
  • Generalized soft bounds model parameters (gamma, gamma_updown, G_max, G_min, deltaG_sp, up_down) = Fitted per device from open-loop pulse traces
    These parameters define the device model for training simulations (Section 4.7.1).
assumptions (5)
  • domain assumption Mott-Gurney trap-to-trap tunneling describes electron transport in the CMO layer
    Equation (6) is assumed as the transport mechanism; parameters are fitted, and the model is used to interpret device behavior.
  • ad hoc to paper Conductance relaxation is independent of programmed conductance and follows a linear trend in log time
    Observed on a subset of states over 1 hour and on one state over 1 week; extrapolated to all states and 10 years without a physical retention model.
  • domain assumption The FEM simulation with an effective 200x200 nm2 area represents the physical device
    The simulation geometry is described in Fig. S1; the effective area is chosen to reduce computational cost and is not directly validated against measurements at this scale.
  • ad hoc to paper Device-to-device variability can be modeled with multivariate Gaussian distributions over the fitted parameters
    G1 and G2 in Section 4.7.2 are fitted to the 32-device array; no evidence that this captures the full distribution for larger arrays.
  • ad hoc to paper The relaxation extrapolation from 1 week to 10 years is valid
    The linear fits in log time are used to project 10-year conductance distributions, which directly feeds the MVM RMSE claims; this is a statistical extrapolation without physical justification.

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Cite this review

Pith. "Pith review of All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices." pith.science (2026). https://pith.science/paper/2WRRCVEI

@misc{pith2026250204524,
  author       = {Pith},
  title        = {Pith review of: All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/2WRRCVEI}},
  note         = {Machine review of arXiv:2502.04524}
}
read the original abstract

Analog in-memory computing is an emerging paradigm designed to efficiently accelerate deep neural network workloads. Recent advancements have focused on either inference or training acceleration. However, a unified analog in-memory technology platform-capable of on-chip training, weight retention, and long-term inference acceleration-has yet to be reported. This work presents an all-in-one analog AI accelerator, combining these capabilities to enable energy-efficient, continuously adaptable AI systems. The platform leverages an array of analog filamentary conductive-metal-oxide (CMO)/HfOx resistive switching memory cells (ReRAM) integrated into the back-end-of-line (BEOL). The array demonstrates reliable resistive switching with voltage amplitudes below 1.5V, compatible with advanced technology nodes. The array multi-bit capability (over 32 stable states) and low programming noise (down to 10nS) enable a nearly ideal weight transfer process, more than an order of magnitude better than other memristive technologies. Inference performance is validated through matrix-vector multiplication simulations on a 64x64 array, achieving a root-mean-square error improvement by a factor of 20 at 1 second and 3 at 10 years after programming, compared to state-of-the-art. Training accuracy closely matching the software equivalent is achieved across different datasets. The CMO/HfOx ReRAM technology lays the foundation for efficient analog systems accelerating both inference and training in deep neural networks.

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Forward citations

Cited by 2 Pith papers

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Pith tools

Reviewed August 8, 2026 · model on record in the stance chip above.