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The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation

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arxiv 2411.00843 v2 pith:DHJX7HSQ submitted 2024-10-30 cs.LG cs.AIcs.ARcs.CL

Reza Moravej , Saurabh Bodhe , Zhanguang Zhang , Didier Chetelat , Dimitrios Tsaras , Yingxue Zhang , Hui-Ling Zhen , Jianye Hao
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Mingxuan Yuan
This is my paper · ORCID
classification cs.LGcs.AIcs.ARcs.CL
keywords circuitqualitycodedesignsestimationgraphlanguagellms
verification ladder T0 review T1 audit T2 compute T3 formal
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Logic synthesis is a crucial phase in the circuit design process, responsible for transforming hardware description language (HDL) designs into optimized netlists. However, traditional logic synthesis methods are computationally intensive, restricting their iterative use in refining chip designs. Recent advancements in large language models (LLMs), particularly those fine-tuned on programming languages, present a promising alternative. This work proposes augmenting LLMs with predictor networks trained to estimate circuit quality directly from HDL code. To enhance performance, the model is regularized using embeddings from graph neural networks (GNNs) trained on Look-Up Table (LUT) graphs, thereby incorporating lower-level circuit insights. The proposed method demonstrates superior performance compared to existing graph-based RTL-level estimation techniques on the established benchmark OpenABCD, while providing instant feedback on HDL code quality.

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Beyond Tokens: Enhancing RTL Quality Estimation via Structural Graph Learning

    cs.LG 2025-08 conditional novelty 6.0 of 10

    StructRTL uses self-supervised learning on control data flow graphs, plus knowledge distillation from post-mapping netlists, to beat prior LLM-based methods for predicting circuit area and delay from RTL code on a 13,...

  2. VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code

    cs.AR 2025-06 conditional novelty 5.0 of 10

    A method that predicts line-level timing and congestion issues directly from Verilog code using CL-Verilog embeddings and gradient-boosted classifiers.

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