pith. sign in

arxiv: 2606.31217 · v1 · pith:ILDAZQNMnew · submitted 2026-06-30 · ❄️ cond-mat.mtrl-sci

High-Mobility and High-Reliability Top-Gate Oxide Semiconductor Transistors by Oxygen Engineering

Pith reviewed 2026-07-01 05:10 UTC · model grok-4.3

classification ❄️ cond-mat.mtrl-sci
keywords oxide semiconductor transistorstop-gate devicesoxygen engineeringoxygen vacanciesoxygen dimerspositive bias temperature instabilityatomic layer depositionindium-rich oxides
0
0 comments X

The pith

An oxygen-rich fabrication process followed by oxygen-free annealing produces high-mobility, high-reliability top-gate indium-rich oxide transistors stable in hydrogen.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper investigates how oxygen levels during fabrication and annealing affect defects in top-gate atomic-layer-deposited oxide semiconductor transistors. It shows that starting with oxygen-rich conditions suppresses oxygen vacancies and their reaction with hydrogen, while an oxygen-free anneal then limits oxygen dimers. This combination delivers transistors that combine high mobility with strong positive-bias-temperature-instability reliability and hydrogen stability. The approach is presented as a way to break the usual mobility-stability trade-off in these devices.

Core claim

An O-rich device fabrication process followed by O-free annealing can effectively achieve TG indium-rich oxide semiconductor transistors with high mobility, high reliability and high stability in hydrogen environment because O-rich process can suppress oxygen vacancies and their interaction with hydrogen, while O-free annealing plays a critical role in minimizing the formation of O-rich defects such as oxygen dimers. Consequently, TG In-rich transistors with high mobility, steep subthreshold slope, and high PBTI reliability at high temperature are demonstrated.

What carries the argument

Oxygen engineering that pairs an oxygen-rich fabrication step with an oxygen-free annealing step to control oxygen vacancies and oxygen-dimer defects.

If this is right

  • The resulting transistors exhibit high mobility, steep subthreshold slope, and high PBTI reliability at elevated temperature.
  • The devices maintain stability when exposed to hydrogen environments.
  • O-rich and O-poor devices display distinct defect populations and different PBTI degradation paths.
  • The oxygen-control sequence overcomes the conventional mobility-stability trade-off in indium-rich oxide transistors.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same oxygen sequence might be tested on other oxide compositions to check whether the defect-suppression benefit generalizes.
  • If the method scales to larger-area or flexible substrates, it could affect process design for display or sensor backplanes.
  • Long-term hydrogen exposure tests beyond the reported conditions would reveal whether the stability persists over device lifetimes.

Load-bearing premise

The observed gains in mobility and reliability are produced specifically by the reduction of oxygen vacancies and oxygen dimers rather than by other differences in the ALD process or device geometry.

What would settle it

Fabricating otherwise identical devices with the oxygen-rich process plus oxygen-free anneal and then measuring defect densities or PBTI shifts that match those of oxygen-poor devices would falsify the claimed mechanism.

read the original abstract

In this work, we investigate the role of oxygen (O) on the performance of top-gate (TG) atomic-layer-deposited (ALD) oxide semiconductor transistors. The results reveal distinct defect characteristics and positive bias temperature instability (PBTI) degradation mechanisms between oxygen-rich (O-rich) and oxygen-deficient (O-poor) devices. It is found that an O-rich device fabrication process followed by O-free annealing can effectively achieve TG indium-rich (In-rich) oxide semiconductor transistors with high mobility, high reliability and high stability in hydrogen environment because O-rich process can suppress oxygen vacancies and their interaction with hydrogen, while O-free annealing plays a critical role in minimizing the formation of O-rich defects such as oxygen dimers (O-O bonds). Consequently, TG In-rich transistors with high mobility, steep subthreshold slope, and high PBTI reliability at high temperature are demonstrated. The understanding of O-rich defects provides a new insight to overcome the mobility-stability trade-off.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 2 minor

Summary. The manuscript claims that an oxygen-rich (O-rich) ALD fabrication process followed by oxygen-free (O-free) annealing enables top-gate indium-rich oxide semiconductor transistors with high mobility, steep subthreshold slope, high PBTI reliability at elevated temperature, and stability in hydrogen environments. It asserts that this process suppresses oxygen vacancies (and their interaction with hydrogen) while minimizing O-rich defects such as oxygen dimers, producing distinct defect characteristics and PBTI mechanisms relative to O-poor devices and thereby overcoming the mobility-stability trade-off.

Significance. If the mechanistic interpretation were validated by direct defect metrology and controlled experiments isolating the proposed defects from other process variables, the work would offer a concrete fabrication route to high-performance oxide transistors suitable for hydrogen-exposed environments, with potential impact on display backplanes and thin-film logic. The experimental comparison of process variants is a standard approach whose value would increase substantially with quantitative defect characterization.

major comments (3)
  1. [Abstract] Abstract: the statements that O-rich and O-poor devices exhibit "distinct defect characteristics and positive bias temperature instability (PBTI) degradation mechanisms" and that the O-rich + O-free process "can effectively achieve" the reported performance gains are presented without any data, error bars, statistical tests, sample sizes, or measurement protocols, so the central claim rests on unverified assertions rather than demonstrated measurements.
  2. [Mechanism paragraph] Mechanism paragraph (referenced in the abstract): the causal attribution of mobility/reliability gains specifically to suppression of oxygen vacancies and oxygen dimers is not isolated from confounding variables in ALD stoichiometry, interface states, film density, or geometry; no independent controls or direct defect metrology (EPR, DLTS, or calibrated XPS/O-vacancy quantification) are described that would test whether the proposed defects, rather than other process-induced changes, dominate the observed improvements.
  3. [Abstract] Abstract: the claim that O-free annealing "plays a critical role in minimizing the formation of O-rich defects such as oxygen dimers (O-O bonds)" is presented as the explanation for high-temperature PBTI reliability, yet the manuscript supplies no spectroscopic or electrical evidence linking dimer density to the measured stability metrics.
minor comments (2)
  1. [Abstract] The abstract would benefit from explicit numerical values (mobility in cm^{2}/Vs, subthreshold slope in mV/dec, PBTI shift in V after specified stress) rather than qualitative descriptors.
  2. Notation for process variants (O-rich vs. O-poor) should be defined consistently with the device fabrication section to avoid ambiguity when comparing results.

Simulated Author's Rebuttal

3 responses · 2 unresolved

We thank the referee for the thorough review and constructive feedback. We address each major comment below, clarifying the evidence from our electrical and reliability characterizations while acknowledging limitations in direct defect metrology.

read point-by-point responses
  1. Referee: [Abstract] Abstract: the statements that O-rich and O-poor devices exhibit "distinct defect characteristics and positive bias temperature instability (PBTI) degradation mechanisms" and that the O-rich + O-free process "can effectively achieve" the reported performance gains are presented without any data, error bars, statistical tests, sample sizes, or measurement protocols, so the central claim rests on unverified assertions rather than demonstrated measurements.

    Authors: The abstract is a concise summary of results presented in detail in the manuscript body, including comparative transfer curves, mobility values, subthreshold slopes, PBTI shifts at elevated temperatures, and hydrogen exposure stability for multiple O-rich and O-poor device variants. We agree that the abstract can be strengthened by incorporating key quantitative metrics and will revise it accordingly to reference the supporting data and protocols more explicitly. revision: partial

  2. Referee: [Mechanism paragraph] Mechanism paragraph (referenced in the abstract): the causal attribution of mobility/reliability gains specifically to suppression of oxygen vacancies and oxygen dimers is not isolated from confounding variables in ALD stoichiometry, interface states, film density, or geometry; no independent controls or direct defect metrology (EPR, DLTS, or calibrated XPS/O-vacancy quantification) are described that would test whether the proposed defects, rather than other process-induced changes, dominate the observed improvements.

    Authors: Our conclusions rest on systematic electrical comparisons across process splits (O-rich vs. O-poor ALD combined with O-free annealing), which produce consistent differences in mobility, subthreshold behavior, PBTI kinetics, and hydrogen immunity. These outcomes support the role of vacancy suppression and dimer minimization. We acknowledge that the study relies on indirect electrical inference rather than direct metrology such as EPR or DLTS, and no additional independent controls beyond the reported process variants are included. revision: no

  3. Referee: [Abstract] Abstract: the claim that O-free annealing "plays a critical role in minimizing the formation of O-rich defects such as oxygen dimers (O-O bonds)" is presented as the explanation for high-temperature PBTI reliability, yet the manuscript supplies no spectroscopic or electrical evidence linking dimer density to the measured stability metrics.

    Authors: The inference is drawn from the superior high-temperature PBTI stability observed exclusively in the O-rich + O-free process relative to other variants, alongside distinct degradation kinetics that differ from O-poor devices. This electrical differentiation is presented as evidence for altered defect populations. The manuscript does not include spectroscopic measurements of dimer density or direct quantitative correlation to PBTI metrics. revision: no

standing simulated objections not resolved
  • Absence of direct defect metrology (EPR, DLTS, or calibrated XPS) to isolate oxygen vacancies and dimers from other process variables.
  • Lack of spectroscopic evidence or quantitative electrical metrics directly linking oxygen dimer density to PBTI stability.

Circularity Check

0 steps flagged

No circularity: purely experimental claims with no derivations or self-referential reductions

full rationale

The paper is an experimental materials/device study. The abstract and provided text contain no equations, fitted parameters, predictions derived from models, or self-citations that bear the central claim. The performance attribution to oxygen-vacancy and oxygen-dimer suppression is presented as an interpretation of process-variant results rather than a mathematical derivation that reduces to its own inputs by construction. No instances of self-definitional logic, fitted-input-as-prediction, uniqueness theorems imported from prior author work, or ansatz smuggling appear. This is the normal case of a self-contained experimental report; concerns about metrology or alternative variables belong to evidence strength, not circularity.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on standard domain assumptions about how oxygen content controls vacancy and dimer formation in oxide semiconductors; no free parameters or new entities are introduced in the abstract.

axioms (1)
  • domain assumption Oxygen-rich ALD conditions suppress oxygen vacancies while oxygen-free annealing suppresses oxygen dimers, and these defects are the dominant cause of the observed mobility and PBTI differences.
    This premise is invoked to explain why the described process sequence produces the reported performance gains.

pith-pipeline@v0.9.1-grok · 5711 in / 1298 out tokens · 35280 ms · 2026-07-01T05:10:04.550022+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

44 extracted references · 44 canonical work pages

  1. [1]

    BEOL-Compatible High-Performance a-IGZO Transistors with Record high Ids,max= 1207 μA/μm and on-off ratio exceeding 1011 at Vds = 1V,

    Q. Li et al., “BEOL-Compatible High-Performance a-IGZO Transistors with Record high Ids,max= 1207 μA/μm and on-off ratio exceeding 1011 at Vds = 1V,” in IEDM Tech. Dig. , p. 2-7, 2022, doi: 10.1109/IEDM45625.2022.10019448

  2. [2]

    Record-Low Metal to Semiconductor Contact Resistance in Atomic-Layer-Deposited In2O3 TFTs Reaching the Quantum Limit,

    C. Niu et al., “Record-Low Metal to Semiconductor Contact Resistance in Atomic-Layer-Deposited In2O3 TFTs Reaching the Quantum Limit,” in IEDM Tech. Dig. , p. 37-2, 2023, doi: 10.1109/IEDM45741.2023.10413708

  3. [3]

    Ultrahigh Bias Stability of ALD In2O3 FETs Enabled by High Temperature O2 Annealing,

    K. Hikake et al., “A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel and InSnOx Electrode with Normally-off Operation, High Mobility and Reliability for 3D Integrated Devices,” in Proc. Symp. VLSI Technol. , p. T14-1, 2023, doi: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185234

  4. [4]

    Ultrahigh Bias Stability of ALD In2O3 FETs Enabled by High Temperature O2 Annealing,

    W. Kim et al., “Demonstration of crystalline IGZO transistor with high thermal stability for memory applications,” in Proc. Symp. VLSI Technol., p. T17-4, 2023, doi: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185258

  5. [5]

    Unraveling BTI in IGZO devices: Impact of device architecture, channel film deposition method and stoichiometry/phase, and device operating conditions,

    S. Fujii et al., “Oxide-semiconductor Channel Transistor DRAM (OCTRAM) with 4F2 Architecture,” in IEDM Tech. Dig., p. 6-1, 2024, doi: 10.1109/IEDM50854.2024.10873368

  6. [6]

    First Direct Observation of Two Different Hydrogen- Related Processes Corresponding to the Negative VTH Shift Under PBTI Stress in IGZO Transistors by Pd Hydrogen Spillover,

    K. H. Chiang et al., “Integration of 0.75 V VDD Oxide-Semiconductor 1T1C Memory with Advanced Logic for An Ultra-Low-Power Low- Latency Cache Solution,” in Proc. Symp. VLSI Technol., p. T2-1, 2025, doi: 10.23919/VLSITECHNOLOGYANDCIR65189.2025.11074854

  7. [7]

    T. C. Chiang, Y. C. Chang, C. R. Huang, C. H. Hsu, and P. T. Liu, “First Demonstration of BEOL-Compatible ALD-Deposited 2 nm-Thick Indium-Tungsten-Tin-Oxide (IWTO) TFTs with Superior Short- Channel Electrical Characteristics: Achieving Enhancement-Mode VTH, ION/OFF >1010, SS~63.3 mV/dec,” in Proc. Symp. VLSI Technol., p. T12- 1, 2025, doi: 10.23919/VLSITE...

  8. [8]

    Understanding and modelling the PBTI reliability of thin-film IGZO transistors,

    A. Chasin et al., “Understanding and modelling the PBTI reliability of thin-film IGZO transistors,” in IEDM Tech. Dig., p. 31-1, 2021, doi: 10.1109/IEDM19574.2021.9720666

  9. [9]

    High-mobility hydrogenated polycrystalline In2O3 (In2O3:H) thin-film transistors,

    Y. Magari, T. Kataoka, W. Yeh, and M. Furuta, “High-mobility hydrogenated polycrystalline In2O3 (In2O3:H) thin-film transistors,” Nat. Commun., vol. 13, no. 1078, 2022, doi: 10.1038/s41467-022-28480-9

  10. [10]

    Ultrahigh Bias Stability of ALD In2O3 FETs Enabled by High Temperature O2 Annealing,

    Z. Zhang, Z. Lin, C. Niu, M. Si, M. A. Alam, and P. D. Ye, “Ultrahigh Bias Stability of ALD In2O3 FETs Enabled by High Temperature O2 Annealing,” in Proc. Symp. VLSI Technol., p. T11-3, 2023, doi: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185292

  11. [11]

    High-Performance Indium-Based Oxide Transistors with Multiple Channels Through Nanolaminate Structure Fabricated by Plasma- Enhanced Atomic Layer Deposition,

    M. H. Cho, C. H. Choi, M. J. Kim, J. S. Hur, T. Kim, and J. K. Jeong, “High-Performance Indium-Based Oxide Transistors with Multiple Channels Through Nanolaminate Structure Fabricated by Plasma- Enhanced Atomic Layer Deposition,” ACS Appl. Mater. Interfaces, vol. 15, no. 15, p. 19137, 2023, doi: 10.1021/acsami.3c00038

  12. [12]

    An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications,

    Q. Jiang, K. Jana, K. Toprasertpong, S. Liu, and H. S. P. Wong, “Positive Bias Stress Measurement Guideline and Band Analysis for Evaluating Instability of Oxide Semiconductor Transistors,” in Proc. Symp. VLSI Technol., p. T16.2, 2024, doi: 10.1109/VLSITECHNOLOGYANDCIR46783.2024.10631369

  13. [13]

    Unraveling BTI in IGZO devices: Impact of device architecture, channel film deposition method and stoichiometry/phase, and device operating conditions,

    A. Chasin et al., “Unraveling BTI in IGZO devices: Impact of device architecture, channel film deposition method and stoichiometry/phase, and device operating conditions,” in IEDM Tech. Dig., p. 34-2, 2024, doi: 10.1109/IEDM50854.2024.10873388

  14. [14]

    First Direct Observation of Two Different Hydrogen- Related Processes Corresponding to the Negative VTH Shift Under PBTI Stress in IGZO Transistors by Pd Hydrogen Spillover,

    Z. Lin et al., “First Direct Observation of Two Different Hydrogen- Related Processes Corresponding to the Negative VTH Shift Under PBTI Stress in IGZO Transistors by Pd Hydrogen Spillover,” in Proc. Symp. VLSI Technol. , p. T17-4, 2025, doi: 10.23919/VLSITECHNOLOGYANDCIR65189.2025.11075056

  15. [15]

    In2O3–ZnO Superlattice Transistors by Atomic Layer Deposition with High Field-Effect Mobility,

    Z. Wang et al., “In2O3–ZnO Superlattice Transistors by Atomic Layer Deposition with High Field-Effect Mobility,” IEEE Electron Device Lett., vol. 46, no. 3, p. 412, 2025, doi: 10.1109/LED.2025.3532673

  16. [16]

    Mobility–stability trade-off in oxide thin-film transistors,

    Y.-S. Shiah et al., “Mobility–stability trade-off in oxide thin-film transistors,” Nat. Electron., vol. 4, p. 800, 2021, doi:10.1038/s41928- 021-00671-0

  17. [17]

    Hydrogen bistability as the origin of photo-bias-thermal instabilities in amorphous oxide semiconductors,

    Y. Kang et al., “Hydrogen bistability as the origin of photo-bias-thermal instabilities in amorphous oxide semiconductors,” Adv. Electron. Mater., vol. 1, no. 7, p. 140006, 2015, doi: 10.1002/aelm.201400006

  18. [18]

    Hydrogen anion and subgap states in amorphous In–Ga–Zn–O thin films for TFT applications,

    J. Bang, S. Matsuishi, H. Hosono, “Hydrogen anion and subgap states in amorphous In–Ga–Zn–O thin films for TFT applications,” Appl. Phys. Lett., vol. 110, no. 23, p. 232105, 2017, doi: 10.1063/1.4985627

  19. [19]

    Oxygen vacancies in ZnO,

    A. Janotti, and C. G. Van De Walle, “Oxygen vacancies in ZnO,” Appl. Phys. Lett., vol. 87, no. 12, p. 122102, 2005, doi: 10.1063/1.2053360

  20. [20]

    Hydrogen multicentre bonds,

    A. Janotti, and C. G. Van De Walle, “Hydrogen multicentre bonds,” Nat. Mater., vol. 6, P. 44, 2007, doi: 10.1038/nmat1795

  21. [21]

    Multiple effects of hydrogen on InGaZnO thin-film transistor and the hydrogenation-resistibility enhancement,

    W. Pan et al., “Multiple effects of hydrogen on InGaZnO thin-film transistor and the hydrogenation-resistibility enhancement,” J. Alloys Compd., vol. 947, p. 169509, 2023, doi: 10.1016/j.jallcom.2023.169509

  22. [22]

    The Role of Oxygen Vacancy and Hydrogen on the PBTI Reliability of ALD IGZO Transistors and Process Optimization,

    Z. Lin et al., “The Role of Oxygen Vacancy and Hydrogen on the PBTI Reliability of ALD IGZO Transistors and Process Optimization,” IEEE Trans. Electron Devices, vol. 71, no. 5, p. 3002, 2024, doi: 10.1109/TED.2024.3374247

  23. [23]

    Unraveling BTI in IGZO devices: Impact of device architecture, channel film deposition method and stoichiometry/phase, and device operating conditions,

    G. Liu et al., “Revealing the Impact of Hydrogen (H) on NBTI/PBTI of IGZTO FETs Under DC and AC Stress: Deep Dive into H Dynamics and Advanced Modeling,” in IEDM Tech. Dig., p. 34-3, 2024, doi: 10.1109/IEDM50854.2024.10873553

  24. [24]

    M. Si, A. Charnas, Z. Lin, and P. D. Ye, “Enhancement-Mode Atomic- Layer-Deposited In2O3 Transistors with Maximum Drain Current of 2.2 A/mm at Drain Voltage of 0.7 V by Low-Temperature Annealing and Stability in Hydrogen Environment,” IEEE Trans. Electron Devices, vol. 68, no. 3, p.1075, 2021, doi: 10.1109/TED.2021.3053229

  25. [25]

    C. H. Choi et al., “High-Performance Indium Gallium Tin Oxide Transistors with an Al2O3 Gate Insulator Deposited by Atomic Layer Deposition at a Low Temperature of 150℃: Roles of Hydrogen and Excess Oxygen in the Al2O3 Dielectric Film,” ACS Appl. Mater. Interfaces, vol. 13, no. 24, p. 28451, 2021, doi: 10.1021/acsami.1c04210

  26. [26]

    Remarkable Stability Improvement with a High- Performance PEALD-IZO/IGZO Top-Gate Thin-Film Transistor via Modulating Dual-Channel Effects,

    Y.-S. Kim et al., “Remarkable Stability Improvement with a High- Performance PEALD-IZO/IGZO Top-Gate Thin-Film Transistor via Modulating Dual-Channel Effects,” Adv. Mater. Interfaces, vol. 9, no. 16, p. 2200501, 2022, doi: 10.1002/admi.202200501

  27. [27]

    High-Performance Short-Channel Top-Gate Indium-Tin- Oxide Transistors by Optimized Gate Dielectric,

    C. Gu et al., “High-Performance Short-Channel Top-Gate Indium-Tin- Oxide Transistors by Optimized Gate Dielectric,” IEEE Electron Device Lett., vol. 44, no. 5, p. 837, 2023, doi: 10.1109/LED.2023.3262684

  28. [28]

    First Demonstration of Top-Gate Enhancement-Mode ALD In2O3 FETs with High Thermal Budget of 600℃ for DRAM Applications,

    J.-Y. Lin et al., “First Demonstration of Top-Gate Enhancement-Mode ALD In2O3 FETs with High Thermal Budget of 600℃ for DRAM Applications,” IEEE Electron Device Lett., vol. 45, no. 10, p. 1851, 2024, doi: 10.1109/LED.2024.3442729

  29. [29]

    Abnormal Positive Shift of Threshold Voltage in Praseodymium-Doped InZnO-TFTs Under Negative Bias Illumination Temperature Stress,

    Y. Han et al., “Abnormal Positive Shift of Threshold Voltage in Praseodymium-Doped InZnO-TFTs Under Negative Bias Illumination Temperature Stress,” IEEE Trans. Electron Devices, vol. 71, no. 3, p. 1951, 2024, doi: 10.1109/TED.202-4.3359160

  30. [30]

    Role of Oxygen Deficiencies on the Stability of Indium Tin Oxide (ITO) Transistors,

    S. Wahid et al., “Role of Oxygen Deficiencies on the Stability of Indium Tin Oxide (ITO) Transistors,” IEEE Electron Device Lett., vol. 46, no. 9, p. 1553, 2025, doi: 10.1109/LED.2025.3587706

  31. [31]

    In-situ Surface Energy Engineering for ALD-Derived Highly Reliable Top Gate In2O3 Thin-Film Transistors,

    J. E. Oh et al., “In-situ Surface Energy Engineering for ALD-Derived Highly Reliable Top Gate In2O3 Thin-Film Transistors,” IEEE Electron Device Lett., vol. 46, no. 11, p. 2050, 2025, doi: 10.1109/LED.2025.3606470

  32. [32]

    Process design for improvement in device performance of top-gate TFTs using In-Sn-Zn-O channels prepared by thermal atomic-layer deposition,

    J.-H. Yoo et al., “Process design for improvement in device performance of top-gate TFTs using In-Sn-Zn-O channels prepared by thermal atomic-layer deposition,” Mater. Sci. Semicond. Process., vol. 190, p. 109324, 2025, doi: 10.1016/j.mssp.2025.109324

  33. [33]

    Multi-Channel, Amorphous Oxide Thin-Film Transistor Exhibiting High Mobility of 67 cm2 V−1 s−1 and Excellent Stability,

    M. M. Billah et al., “Multi-Channel, Amorphous Oxide Thin-Film Transistor Exhibiting High Mobility of 67 cm2 V−1 s−1 and Excellent Stability,” Adv. Electron. Mater., vol. 11, no. 8, p. 2400766, 2025, doi: 10.1002/aelm.202400766

  34. [34]

    High Mobility and Robust Top-Gate In2O3 Thin Film Transistor by Ozone-Based Treatment,

    C.-S. Huang et al., “High Mobility and Robust Top-Gate In2O3 Thin Film Transistor by Ozone-Based Treatment,” IEEE J. Electron Devices Soc., vol. 13, p. 1112, 2025, doi: 10.1109/JEDS.2025.3627495

  35. [35]

    Improved electrical performance and stability of top-gated indium–tin–zinc–oxide thin-film transistors via oxygen plasma treatment,

    J. Park et al., “Improved electrical performance and stability of top-gated indium–tin–zinc–oxide thin-film transistors via oxygen plasma treatment,” Semicond. Sci. Technol., vol. 40, no. 11, p. 115013, 2025, doi: 10.1088/1361-6641/ae1869

  36. [36]

    Reliability Improvement of High Mobility Oxide TFTs Based on Hydrogen-Resistant PEALD Al2O3 Gate Insulators Grown with N2O Plasma,

    S.-H. Kim et al., “Reliability Improvement of High Mobility Oxide TFTs Based on Hydrogen-Resistant PEALD Al2O3 Gate Insulators Grown with N2O Plasma,” ACS Appl. Mater. Interfaces, vol. 17, no. 9, p. 14168, 2025, doi: 10.1021/acsami.4c18561

  37. [37]

    The Critical Role of Passivation Layer and Semiconductor Interface on the Hydrogen Stability of ALD IGZO Transistors,

    Z. Lin et al., “The Critical Role of Passivation Layer and Semiconductor Interface on the Hydrogen Stability of ALD IGZO Transistors,” IEEE Trans. Electron Devices, vol. 72, no. 8, p. 4138, 2025, doi: 10.1109/TED.2025.3575400

  38. [38]

    Top-Gate Atomic-Layer-Deposited Oxide Semiconductor Transistors With Large Memory Window and Non- Ferroelectric HfO2 Gate Stack,

    K. Jiang et al., “Top-Gate Atomic-Layer-Deposited Oxide Semiconductor Transistors With Large Memory Window and Non- Ferroelectric HfO2 Gate Stack,” IEEE Electron Device Lett., vol. 46, no. 8, p. 1353, 2025, doi: 10.1109/LED.2025.3581599

  39. [39]

    Near-Ideal Top-Gate Controllability of InGaZnO Thin-Film Transistors by Suppressing Interface Defects with an Ultrathin Atomic Layer Deposited Gate Insulator,

    J. Li et al., “Near-Ideal Top-Gate Controllability of InGaZnO Thin-Film Transistors by Suppressing Interface Defects with an Ultrathin Atomic Layer Deposited Gate Insulator,” ACS Appl. Mater. Interfaces, vol. 15, no. 6, p. 8666, 2023, doi:10.1021/acsami.2c20176

  40. [40]

    Ultra-thin top-gate insulator of atomic-layer-deposited HfOx for amorphous InGaZnO thin-film transistors,

    Y. Guan et al., “Ultra-thin top-gate insulator of atomic-layer-deposited HfOx for amorphous InGaZnO thin-film transistors,” Appl. Surf. Sci., vol. 625, no. 157177, 2023, doi:10.1016/j.apsusc.2023.157177

  41. [41]

    An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications,

    J.-E. Yang et al., “A-IGZO FETs with High Current and Remarkable Stability for Vertical Channel Transistor (VCT)/3D DRAM Applications,” in Proc. Symp. VLSI Technol., p. T4.5, 2024, doi: 10.1109/VLSITechnologyandCir46783.2024.10631550

  42. [42]

    Synergistic Effects of Deposition Temperatures for Active and Gate Insulator of Top-Gate Thin-Film Transistors Using InGaZnO Channels Prepared by Thermal Atomic-Layer Deposition,

    Y. J. Seo, J. W. Lee, Y. H. Kwon, N. J. Seong, K. J. Choi, and S. M. Yoon, “Synergistic Effects of Deposition Temperatures for Active and Gate Insulator of Top-Gate Thin-Film Transistors Using InGaZnO Channels Prepared by Thermal Atomic-Layer Deposition,” ACS Appl. Electron. Mater., vol. 6, no. 10, p. 7563, 2024, doi: 10.1021/acsaelm.4c01380

  43. [43]

    Enhancement in Performance and Reliability of Fully Transparent a-IGZO Top-Gate Thin-Film Transistors by a Two-Step Annealing Treatment,

    S. Zheng et al., “Enhancement in Performance and Reliability of Fully Transparent a-IGZO Top-Gate Thin-Film Transistors by a Two-Step Annealing Treatment,” Nanomater., vol. 15, no. 6, p. 460, 2025, doi:10.3390/nano15060460

  44. [44]

    X. Li et al., “First Demonstration of Atomic-Interlayer-Tuning Driven by First Principles Calculations and Atomic Layer Deposition towards High Thermal Stable BEOL IGZO-FETs with SS=62mV/dec, PBTI < 7mV@ 3MV/cm and 353K,” in Proc. Symp. VLSI Technol., p. T17-3, 2025, doi: 10.23919/VLSITechnologyandCir65189.2025.11075061