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arxiv: 2401.07054 · v1 · pith:KPFHNJH7 · submitted 2024-01-13 · quant-ph · cs.AI

A Reinforcement Learning Environment for Directed Quantum Circuit Synthesis

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classification quant-ph cs.AI
keywords quantumcircuitsenvironmentcircuitlearningstatesqubitreinforcement
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With recent advancements in quantum computing technology, optimizing quantum circuits and ensuring reliable quantum state preparation have become increasingly vital. Traditional methods often demand extensive expertise and manual calculations, posing challenges as quantum circuits grow in qubit- and gate-count. Therefore, harnessing machine learning techniques to handle the growing variety of gate-to-qubit combinations is a promising approach. In this work, we introduce a comprehensive reinforcement learning environment for quantum circuit synthesis, where circuits are constructed utilizing gates from the the Clifford+T gate set to prepare specific target states. Our experiments focus on exploring the relationship between the depth of synthesized quantum circuits and the circuit depths used for target initialization, as well as qubit count. We organize the environment configurations into multiple evaluation levels and include a range of well-known quantum states for benchmarking purposes. We also lay baselines for evaluating the environment using Proximal Policy Optimization. By applying the trained agents to benchmark tests, we demonstrated their ability to reliably design minimal quantum circuits for a selection of 2-qubit Bell states.

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

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    Generative optimization of quantum embedding circuits improves supervised classification on some datasets, with derived bounds showing performance saturation governed by Wasserstein distance of the classical input data.

  2. Investigation of Automated Design of Quantum Circuits for Imaginary Time Evolution Methods Using Deep Reinforcement Learning

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    DDQN reinforcement learning automates VITE circuit design, producing circuits with ~37% fewer gates and ~43% less depth than hardware-efficient ansatze for Max-Cut while reaching Full-CI for H2 with shallower depth.