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arxiv: 1906.11175 · v1 · pith:NATROM7Vnew · submitted 2019-06-26 · 💻 cs.AR · cs.PF

FPGA-based Multi-Chip Module for High-Performance Computing

Yann Beilliard , Maxime Godard , Aggelos Ioannou , Astrinos Damianakis , Michael Ligerakis , Iakovos Mavroidis , Pierre-Yves Martinez , David Danovitch
show 2 more authors
Julien Sylvestre Dominique Drouin
This is my paper

Pith reviewed 2026-05-25 14:51 UTC · model grok-4.3

classification 💻 cs.AR cs.PF
keywords FPGAMulti-Chip ModuleMCMExascale computingHigh-speed linksXilinx Zynq Ultrascale+Laminate substrate
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The pith

Multi-chip modules with two Xilinx Zynq Ultrascale+ MPSoCs were fabricated on 68.5 mm x 55 mm substrates and passed all defect and 10 Gbps link tests for Exascale use.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that advanced laminate-based MCMs can integrate two Xilinx Zynq Ultrascale+ MPSoCs without manufacturing defects while supporting stable high-speed operation. This addresses the integration barriers that currently block the density and efficiency needed for Exascale systems. Acoustic microscopy, x-ray, cross-section, and Thermo-Moire checks found no voids, shorts, delamination, cracks, or warpage. Memory tests at 1866 MHz and 2133 MHz succeeded on the daughter-board SODIMMs, and all intra-board links remained error-free at 10 Gbps under 31-bit PRBS patterns.

Core claim

We report successful fabrication of first ExaNoDe's MCM prototypes dedicated to Exascale computing applications. Each MCM was composed of 2 Xilinx Zynq Ultrascale+ MPSoC, assembled on advanced 68.5 mm x 55 mm laminate substrates specifically designed and fabricated for the project. Acoustic microscopy, x-ray, cross-section and Thermo-Moire investigations revealed no voids, shorts, delamination, cracks or warpage issues. Two MCMs were mounted on a daughter board by FORTH for testing purposes. The DDR memories on the 4 SODIMMs of the daughter board were successfully tested by running extensive Xilinx memory tests with clock frequencies of 1866 MHz and 2133 MHz. All 4 FPGAs were programmed with

What carries the argument

The MCM that places two Xilinx Zynq Ultrascale+ MPSoCs on a custom 68.5 mm x 55 mm laminate substrate to provide the high-density integration and 10 Gbps intra-board links required for Exascale workloads.

If this is right

  • MCMs can be mounted on daughter boards and still pass DDR memory validation at 2133 MHz.
  • All intra-board high-speed links between the four FPGAs remain stable at 10 Gbps even with demanding 31-bit PRBS patterns.
  • The chosen laminate substrate and assembly process produce modules free of voids, shorts, delamination, cracks, and warpage.
  • The approach supplies a concrete hardware building block that meets the density and power-efficiency targets stated for Exascale.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same substrate and assembly techniques could be extended to modules containing more than two MPSoCs without introducing new defect classes.
  • Stable 10 Gbps links on the tested board layout suggest that similar routing on larger systems would maintain signal integrity.
  • Absence of warpage under Thermo-Moire testing implies the modules can tolerate the thermal cycling expected in continuous Exascale operation.

Load-bearing premise

That passing the described memory tests at 1866/2133 MHz and PRBS link tests at 10 Gbps demonstrates suitability for actual Exascale application workloads.

What would settle it

Discovery of voids, delamination, cracks, or bit errors on the 10 Gbps links in a second set of fabricated MCMs under the same test conditions.

Figures

Figures reproduced from arXiv: 1906.11175 by Aggelos Ioannou, Astrinos Damianakis, David Danovitch, Dominique Drouin, Iakovos Mavroidis, Julien Sylvestre, Maxime Godard, Michael Ligerakis, Pierre-Yves Martinez, Yann Beilliard.

Figure 1
Figure 1. Figure 1: Schematic representations of a) the full ExaNoDe’s [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 3
Figure 3. Figure 3: a) Top-down x-ray image of a soldered FPGA showing no [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Photograph of a fully assembled daughter board used for [PITH_FULL_IMAGE:figures/full_fig_p002_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Photograph of an assembled MCM Mk I, composed of 2 [PITH_FULL_IMAGE:figures/full_fig_p002_5.png] view at source ↗
read the original abstract

Current integration, architectural design and manufacturing technologies are not suited for the computing density and power efficiency requested by Exascale computing. New approaches in hardware architecture are thus needed to overcome the technological barriers preventing the transition to the Exascale era. In that scope, we report successful fabrication of first ExaNoDe's MCM prototypes dedicated to Exascale computing applications. Each MCM was composed of 2 Xilinx Zynq Ultrascale+ MPSoC, assembled on advanced 68.5 mm x 55 mm laminate substrates specifically designed and fabricated for the project. Acoustic microscopy, x-ray, cross-section and Thermo-Moire investigations revealed no voids, shorts, delamination, cracks or warpage issues. Two MCMs were mounted on a daughter board by FORTH for testing purposes. The DDR memories on the 4 SODIMMs of the daughter board were successfully tested by running extensive Xilinx memory tests with clock frequencies of 1866 MHz and 2133 MHz. All 4 FPGAs were programmed with the Xilinx integrated bit error ratio test (IBERT) tailored for this board for links testing. All intra-board high-speed links between all FPGAs were stable at 10 Gbps, even under the more demanding 31-bit PRBS (Pseudorandom Binary Sequence) tests.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 2 minor

Summary. The manuscript reports successful fabrication of the first ExaNoDe MCM prototypes for Exascale computing. Each MCM integrates two Xilinx Zynq Ultrascale+ MPSoCs on a custom 68.5 mm × 55 mm laminate substrate. Post-assembly inspections (acoustic microscopy, x-ray, cross-section, Thermo-Moire) found no voids, shorts, delamination, cracks or warpage. When two MCMs were mounted on a daughter board, DDR memories on four SODIMMs passed Xilinx memory tests at 1866 MHz and 2133 MHz, and all intra-board high-speed links between the four FPGAs passed 10 Gbps operation under 31-bit PRBS using the Xilinx IBERT tool.

Significance. If the reported outcomes hold, the work supplies concrete evidence that advanced laminate-based MCM assembly can produce defect-free, electrically functional multi-FPGA modules at the scale needed for high-density Exascale platforms. The use of complementary non-destructive and destructive inspection methods plus standard electrical validation constitutes a necessary first milestone; the absence of workload-level or long-term reliability data is consistent with the paper’s limited scope.

major comments (1)
  1. [Abstract] Abstract and § (testing description): the claims of “successful” memory and link tests are stated without quantitative metrics (bit-error rates, test duration, temperature/voltage corners, or pass/fail criteria), which are required to substantiate the central assertion that the MCMs are electrically viable.
minor comments (2)
  1. The manuscript should include a brief methods subsection or supplementary table listing exact test parameters, number of devices tested, and any observed margins.
  2. Figure captions and text should explicitly state the number of MCMs fabricated versus the number electrically tested.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive comment and positive overall assessment. We address the single major comment below and will revise the manuscript accordingly.

read point-by-point responses

  1. Referee: [Abstract] Abstract and § (testing description): the claims of “successful” memory and link tests are stated without quantitative metrics (bit-error rates, test duration, temperature/voltage corners, or pass/fail criteria), which are required to substantiate the central assertion that the MCMs are electrically viable.

    Authors: We agree that the abstract and testing description would be strengthened by additional quantitative detail. The reported tests used the standard Xilinx memory test suite (which performs extensive read/write verification) at 1866 MHz and 2133 MHz, and the IBERT tool configured for 31-bit PRBS at 10 Gbps; both suites report pass/fail status with implicit error detection. No errors were observed, but exact BER figures, test durations, and corner-case data were not recorded in the original submission because the paper’s scope centers on fabrication yield and basic electrical functionality rather than full characterization. We will revise the abstract and the testing section to state the available parameters explicitly (frequencies, PRBS pattern, tool versions) and to note that the tests passed with zero detected errors under the conditions described. revision: yes

Circularity Check

0 steps flagged

No significant circularity; purely descriptive fabrication report

full rationale

The paper contains no derivations, equations, predictions, fitted parameters, or theoretical claims that could reduce to inputs by construction. It is a standard experimental report describing MCM fabrication, assembly, and post-fabrication validation (acoustic microscopy, x-ray, Thermo-Moire, Xilinx memory tests at 1866/2133 MHz, and 10 Gbps PRBS link tests). All reported outcomes are direct measurements from the described procedures with no self-citation load-bearing steps or ansatzes. This is the most common honest finding for hardware prototype papers.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

This is an empirical hardware fabrication report containing no mathematical derivations, fitted parameters, background axioms, or postulated entities.

pith-pipeline@v0.9.0 · 5802 in / 1078 out tokens · 28963 ms · 2026-05-25T14:51:23.393262+00:00 · methodology

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Reference graph

Works this paper leans on

2 extracted references · 2 canonical work pages

  1. [1]

    for card attach with a 1 µm pitch BGA. b. Electrical tests The assembled MCMs Mk I were mounted on daughter boards (DB) by FORTH with a standard reflow process. As shown in Fig 5, each DB was plugged into a small carrier board called Minifeeder, which provides 10 high-speed small form-factor pluggable (SFP+) transceivers, 1 GigE interface, universal async...

    work page 2020

  2. [2]

    Rigo et al., ECDSD, 2017, pp

    A. Rigo et al., ECDSD, 2017, pp. 486–493

    work page 2017