REVIEW 4 major objections 7 minor 2 cited by
TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion
T0 review · 4 major / 7 minor · reviewed 2026-08-03 · deepseek-v4-flash
Pith's one-line read This paper claims that closing the detection loop—feeding GNN verdicts back into an LLM that re-inserts hardware Trojans—systematically produces diverse, functionally correct Trojans that evade modern GNN detectors up to 83.33% of the time,
desk verdict Closed-loop HT generation is a real idea, but the 'functionally correct' claim rests on compile checks only, and the 83.33% evasion number is an oracle-selected upper bound. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The machinery is a gated feedback loop: given high-level Trojan specifications, LLM agents analyze the target RTL, select insertion points, generate modified Verilog, then pass through a compile-and-repair smoke test; surviving designs are scored by a GNN-based detector, and detected designs are returned to the LLM with instructions to minimize changes to the data-flow graph and syntax tree. The loop runs up to four refinement iterations per Trojan. The paper also introduces Robust-GNN4TJ, an ensemble of four graph-neural-network detectors—one per Trojan type—trained on 884 clean designs and 3,536 LLM-generated infected designs, which replaces fragile parsing with a lightweight parser and st
What would settle it
Run cycle-accurate simulation or formal equivalence checking on the generated Trojan-infected RTL against the golden design under normal inputs; finding any output mismatch outside the trigger condition would falsify the functionality-preservation claim, and a sharp drop in evasion when a detector with temporal or functional features is used would show the gap is structural-GNN-specific.
Extended reading notes
Core claim
The central claim is that closing the loop between HT generation and detection—feeding detection results back into an LLM that re-inserts the Trojan—makes evasion easier and more systematic than one-shot generation. On SRAM, AES-128, and UART designs with GPT-4, Gemini-2.5Pro, and LLaMA-3.3-70B, the authors report an aggregate 61.11% evasion rate across 36 insertion combinations, rising to 83.33% with optimal per-design model selection. The improved detector Robust-GNN4TJ—which uses a lightweight parser, a larger training set, a learning-rate scheduler, and a four-model ensemble—raises detection from 0% to 60% on the most challenging generated benchmarks, yet still leaves a large evasion spa
Load-bearing premise
The claim that generated Trojans preserve normal functionality rests on compile-success and prompt-level constraints rather than on simulation, formal equivalence, or testbench-based verification.
Editorial extensions
If this is right
- If a detector's feedback is part of the attack loop, static benchmark evaluation overestimates detector robustness; detection results must be reported under adaptive attack.
- Generated benchmarks like the 36-design corpus can serve as stress tests for next-generation detectors, with metadata on refinement history and detector scores.
- The failure of joint training versus per-HT-type ensemble suggests that detectors should be built per attack class rather than one model for all Trojans.
- Evasion success depends on Trojan type: performance-degradation Trojans evade more often because they can be realized as auxiliary logic with minimal interference, while information-leakage and denial-of-service Trojans alter control paths and are more detectable.
- The 'optimal' 83.33% evasion across models indicates that multiple LLMs have complementary strengths; an attacker with access to a portfolio of LLMs is stronger than any single model.
Reading between the lines
- Implicitly, the framework treats compilation as the only correctness gate; if functional simulation or formal equivalence checking were added, many 'functionally correct' claims might shrink, especially for subtle functional-perturbation Trojans.
- The robustness gap may be detector-specific: a detector that uses temporal or functional features (e.g., activation rarity or simulation traces) rather than static graph structure could catch these Trojans, so the 83.33% evasion should not be read as a general claim about all detection approaches.
- The use of synthetic training data from LLM-generated Trojans (3,536 samples) raises a distribution question: detectors trained on LLM-generated attacks may overfit to LLM stylistic patterns, so continued co-evolution is needed to avoid a new form of benchmark overfitting.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The paper introduces TrojanGYM, an agentic LLM-based framework that automatically generates RTL hardware Trojans in a closed loop with a GNN-based detector. Three LLMs (GPT-4, Gemini-2.5Pro, LLaMA-3.3-70B) propose and iteratively refine Verilog modifications based on syntactic compile errors and detector feedback. The authors also propose Robust-GNN4TJ, a re-implementation of GNN4TJ with improved graph extraction, a larger training set, and an ensemble of four HT-type-specific models. They evaluate on SRAM, AES-128, and UART, reporting that Robust-GNN4TJ detects up to 60% of GHOST-generated HTs, and that TrojanGYM-generated HTs achieve up to 83.33% evasion against Robust-GNN4TJ. The paper claims the generated HTs are diverse and functionally correct.
Significance. The paper addresses an important problem: benchmarking hardware Trojan detectors with adaptively generated, LLM-produced Trojans. The detector-in-the-loop idea is timely, and the construction of a larger and more diverse training dataset for GNN-based HT detection is a useful contribution. If the functional-correctness claim can be substantiated and the evaluation made less circular, the framework would provide a valuable stress-test for HT detectors. The paper is relatively candid about the oracle-style selection for the headline evasion number and promises artifact release. However, the central validation gap—the absence of functional equivalence checking—currently limits the conclusions that can be drawn from the reported results.
major comments (4)
- [Section IV-C, IV-E, VII] The claim that generated HTs are 'functionally correct' is not supported by the methodology. Section IV-C describes only compilation smoke tests and up to four LLM repair iterations; no simulation, formal equivalence, or testbench-based functional checks are described. Section IV-E defines a successful run as one that 'passes syntactic checks,' and Section VII's assertion of a 'gated validation loop enforces constraint-aware equivalence' is not backed by any concrete method. Compilation success does not imply preservation of normal functionality: subtle changes to control logic, state initialization, or combinational paths can alter behavior even when the trigger is inactive. This is load-bearing because the 83.33% evasion rate may partly reflect detectors failing on malformed designs rather than on stealthy, functionally correct Trojans. The authors must add simulation/formal equivalenc
- [Section VI-B] The headline 83.33% evasion rate is an oracle-selected upper bound: it is obtained by 'selecting the best-performing model per design' across the three LLMs (Section VI-B). This is a post-hoc optimum, not the performance of a single adversary or of TrojanGYM with a fixed configuration. The abstract's 'up to' phrasing is technically correct, but presenting this number as the central result without clearly separating it from the per-LLM 61.11% average is misleading. The authors should either restructure the claims around the non-oracle numbers or explicitly justify why oracle selection is a meaningful metric for the paper's stated contribution of 'systematically' producing evasive HTs.
- [Section IV-D and VI-B] The evaluation is partly circular: Robust-GNN4TJ is used both as the feedback mechanism inside the generation loop (Section IV-D) and as the benchmark on which the final HTs are evaluated (Section VI-B). The reported evasion rates therefore measure the adversary's ability to exploit oracle access to that specific detector, not an independent estimate of detector robustness. The paper does frame this as an adaptive co-evolution, which is legitimate, but the conclusion that the results 'reveal robustness gaps' in modern GNN detectors should be supported by an evaluation against a held-out detector not used during generation (e.g., the original GNN4TJ, or another GNN trained independently). At minimum, the limitation must be discussed explicitly in the conclusion and abstract.
- [Section V and VI] All reported results appear to come from single runs. LLM-generated RTL is stochastic, and the outcomes in Table III (detected/evaded/syntax error) are likely to vary across independent runs with the same configuration. The quantitative claims (61.11% and 83.33% evasion, detection trends in Fig. 4) are presented without error bars, confidence intervals, or multiple-seed experiments. The authors should repeat the pipeline several times per (LLM, design, HT type) configuration and report the distribution of outcomes, or otherwise justify why a single run per cell is representative.
minor comments (7)
- [Section IV-D] The sentence 'The below list contains representative prompts that help illustrate the process of syntactic checking and feedback to the LLM in case of an error.' appears twice, once before and once after the prompt list. Remove the duplicate.
- [Section V] In the 'Robust-GNN4TJ Setup' paragraph, 'we introduceRobust-GNN4TJ' is missing a space after 'introduce'.
- [Table III] The legend for Table III is confusing: 'N/A : No further attempt (Evaded); Evade; Non-evade.' The symbols ✓ and × are used in the table body; please use a cleaner legend, e.g., '✓: detected, ×: evaded, SE: syntax error, N/A: no further attempt (already evaded).'
- [Fig. 5] The heatmaps use 'NA' to indicate missing variants (e.g., absent A4), but this is only clear from the caption's parenthetical remark. Add an explicit note in the figure itself or the caption that 'NA' denotes non-existent refinement iteration.
- [Abstract and Section I] The line 'Index Terms—hardware Trojans, hardware security, large language models, design automation, cybersecurity.' appears inside the abstract in the full text. Move it to a proper index-term section below the abstract.
- [References] References [15] and [36] are the same paper (VeriGen). Consolidate to a single reference to avoid duplication.
- [Section VI-A] The computation of 'overall detection accuracy of 50%' and 'up to 60%' in the ensemble setting is not fully specified. State the denominator (e.g., across which designs and HT types) and clarify whether the 'excluding HT1' result excludes all HT1 samples from both training and evaluation.
Circularity Check
The headline evasion metric is an adaptive-fit statistic because the same detector is both the generation oracle and the evaluation benchmark; functional-correctness is asserted from syntax-only checks, but no formal derivation is circular.
-
fitted input called prediction
[Section IV-D (GNN-based Detection and Adversarial Refinement) and Section VI-B (Iterative LLM-Based Trojan Generation under Detector Feedback)]
"For each candidate, the detector outputs HT probability. Designs with scores below the threshold are considered stealthy with respect to the current detector and are included in the final corpus. Designs above the threshold are classified as detected and trigger an adversarial refinement loop:"
Stealthiness/evasion is defined by the same detector that provides feedback during generation. The reported 'evasion' rate is the fraction of refinement loops that found a below-threshold design, i.e., a fit-success statistic with respect to the very model being used to steer the LLM. Section VI-B then treats the resulting decrease in detection accuracy as an empirical finding about detector robustness, but this decrease is by construction: the loop is explicitly instructed to minimize DFG/AST changes and evade HW2VEC. The 83.33% figure is further amplified by oracle-style selection over three LLMs, making it an upper bound of an adaptive attack, not an independent estimate of detector weakness.
full rationale
TrojanGYM's formal derivation chain is not circular in the usual sense: there are no equations derived from their own outputs, no load-bearing self-citation chain, and the Robust-GNN4TJ improvement is partly validated on GHOST-generated, feedback-free HTs, which provides independent grounding. The main circularity-adjacent element is that the same detector is embedded in the generation loop and then used as the benchmark; the reported evasion rates are therefore adaptive-attack outcomes rather than independent robustness measurements. The paper discloses this design in Section IV-D, but the abstract's phrasing ('evasion rates against modern GNN-based detectors') overstates the independence of the metric. Separately, the claim that generated HTs are 'functionally correct' is not established: Section IV-C describes only compilation smoke tests and repair rounds, with no simulation, formal equivalence, or testbench-based functional check, and Section VII's reference to a 'gated validation loop enforces constraint-aware equivalence' is not backed by any described equivalence method. That is an unvalidated premise and a correctness risk, but it is not itself a circularity. Overall, the core generation framework has independent content, but the headline evasion number partially reduces to the loop's own acceptance criterion, warranting a moderate score of 4.
Assumptions & free parameters
free parameters (4)
- Maximum refinement iterations =
4
- Detector ensemble size and fusion rule =
4 models, OR fusion
- Training data size =
884 clean VeriGen designs + 3,536 Trojan designs
- Detection threshold =
not stated (implicitly 0.5)
assumptions (6)
- ad hoc to paper Syntactic compilation success is a sufficient gate for functional correctness
- domain assumption LLMs can implement HT plans in synthesizable RTL while preserving intended behavior
- domain assumption Graph structure and t-SNE separability capture Trojan detectability
- domain assumption Detector feedback in the form of logs can be interpreted by LLMs to produce stealthier modifications
- domain assumption Attacker has read-write access to RTL after design
- domain assumption LLM outputs are diverse and non-deterministic enough to represent an attack distribution
Cite this review
Pith. "Pith review of TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion." pith.science (2026). https://pith.science/paper/P6JDLBXR
@misc{pith2026260117178,
author = {Pith},
title = {Pith review of: TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion},
year = {2026},
howpublished = {\url{https://pith.science/paper/P6JDLBXR}},
note = {Machine review of arXiv:2601.17178}
}
read the original abstract
Hardware Trojans (HTs) remain a critical threat because learning-based detectors often overfit to narrow trigger/payload patterns and small, stylized benchmarks. We introduce TrojanGYM, an agentic, LLM-driven framework that automatically curates HT insertions to expose detector blind spots while preserving design correctness. Given high-level HT specifications, a suite of cooperating LLM agents (instantiated with GPT-4, LLaMA-3.3-70B, and Gemini-2.5Pro) proposes and refines RTL modifications that realize diverse triggers and payloads without impacting normal functionality. TrojanGYM implements a feedback-driven benchmark generation loop co-designed with HT detectors, in which constraint-aware syntactic checking and GNN-based HT detectors provide feedback that iteratively refines HT specifications and insertion strategies to better surface detector blind spots. We further propose Robust-GNN4TJ, a new implementation of the GNN4TJ with improved graph extraction, training robustness, and prediction reliability, especially on LLM-generated HT designs. On the most challenging TrojanGYM-generated benchmarks, Robust-GNN4TJ raises HT detection rates from 0% to 60% relative to a prior GNN-based detector. We instantiate TrojanGYM on SRAM, AES-128, and UART designs at RTL level, and show that it systematically produces diverse, functionally correct HTs that reach up to 83.33% evasion rates against modern GNN-based detectors, revealing robustness gaps that are not apparent when these detectors are evaluated solely on existing TrustHub-style benchmarks. Post peer-review, we will release all codes and artifacts.
Figures
Figures from the paper (3 more)
Forward citations
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Reviewed August 3, 2026 · model on record in the stance chip above.
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