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arxiv: 2606.27919 · v1 · pith:PA24KIHEnew · submitted 2026-06-26 · 💻 cs.DC · cs.CR

RAMSES: Secure high-performance computing for sensitive data

Pith reviewed 2026-06-29 02:43 UTC · model grok-4.3

classification 💻 cs.DC cs.CR
keywords high-performance computingdata securityencryptionsensitive databiomedical computingregulatory complianceHPC architectureperformance benchmarks
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The pith

RAMSES shows an HPC platform can keep sensitive data encrypted at every stage while limiting performance loss to acceptable levels.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper describes RAMSES, an HPC system built to process sensitive data at scale by combining hardware memory encryption with file encryption and operating system hardening. Data stays protected at rest, in transit, and during use through AMD processor features, IBM Storage Scale, and Thales CipherTrust tools, all while meeting GDPR, ISO 27001, and FIPS requirements. Multi-factor authentication and layered security measures adapt the environment to stricter demands without breaking existing workflows. Biomedical benchmarks indicate the added protections cause only limited slowdowns. A reader would care because fields that handle private information at large volumes could run demanding calculations without choosing between speed and compliance.

Core claim

RAMSES integrates AMD hardware-based memory encryption with IBM Storage Scale file encryption and Thales CipherTrust management to maintain continuous encryption throughout the data life cycle. It adds advanced operating system hardening and mandatory multi-factor authentication. The resulting platform complies with European General Data Protection Regulation, ISO/IEC 27001, and Federal Information Processing Standards. Benchmark results from the biomedical sector show the performance impact of these measures remains limited, allowing speed and security to coexist in a coherent, flexible, and user-friendly system.

What carries the argument

The continuous encryption stack that protects data at rest, in transit, and in use, combined with OS hardening inside a standard HPC architecture.

If this is right

  • Biomedical research can run large-scale computations on sensitive data without major speed penalties.
  • HPC installations can meet strict data-protection regulations while retaining flexibility for users.
  • Encryption throughout the data life cycle becomes practical in performance-critical environments.
  • Existing HPC software stacks remain usable after the addition of these security layers.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same layered approach might support other domains that need both high computation and privacy, such as financial risk modeling.
  • Ongoing validation against new workloads would be needed to confirm the limited-impact result holds more widely.
  • Integration challenges could arise if the encryption components require frequent updates to stay current with standards.

Load-bearing premise

The chosen encryption stack and hardening steps will continue to deliver acceptable performance and security under production workloads beyond the biomedical benchmarks shown.

What would settle it

Performance measurements on a broader set of production workloads that reveal either large slowdowns or encryption failures despite the described measures would disprove the central claim.

Figures

Figures reproduced from arXiv: 2606.27919 by Christoph Stollwerk, Kamil Tokmakov, Lech Nieroda, Martin Peifer, Michael Commer, Peter Heger, Roland Pabel, Stefan Borowski, Stefan Wesner, Viktor Achter.

Figure 1
Figure 1. Figure 1: GPFS-based file encryption on RAMSES. File encryption is managed through the GPFS kernel module and the Thales CipherTrust Manager for Remote Key Man￾agement (RKM). Two encrypted file sets (fileset a, fileset b) with three files each are shown. Each file is encrypted via its unique File Encryption Key (FEK1-6), which is stored in the file’s extended attributes. FEKs in turn are encrypted by a file set-spec… view at source ↗
Figure 2
Figure 2. Figure 2: Secure vs. traditional HPC workflow on RAMSES. 1: UoC members connect to the UoC network using multi-factor authentication (MFA) based on their IDM credentials and Cisco Duo. 2: Registered HPC users login to RAMSES using multi-factor authentication with an SSH key pair and Cisco Duo. 3: On the frontend node(s), users submit their jobscript for confidential (left side) or traditional computing (right side) … view at source ↗
Figure 3
Figure 3. Figure 3: The RAMSES SSH key upload website. A: UoC members with approved RAMSES account can connect to the RAMSES key upload website (https://ramses -umc.itcc.uni-koeln.de/web-sshkey/login) from within the University network, using their UoC IDM credentials and Cisco Duo. B, C: To improve user experience and security, a JavaScript-Plugin carries out SSH key pair generation and ensures its protection with a strong p… view at source ↗
Figure 4
Figure 4. Figure 4: RAMSES’s security layout. The physical and logical system components of RAMSES are separated into four security levels, S0 to S3, illustrated as concentric circles. Unprivileged users can only access login and compute nodes of the lowest security level, S3 (outer ring). Access to nodes of higher security levels (S0 to S2) is restricted to privileged accounts and implemented through unidirectionality, harde… view at source ↗
Figure 5
Figure 5. Figure 5: Performance of two contrasting workloads under various encryp￾tion regimes. RepeatMasker (top; I/O-heavy) and BWA-MEM2 (bottom; memory￾intensive) runs were carried out in seven different configurations with six replicates each: 1) Standard SMP node without memory and without file encryption (SMP-M⊖F⊖); 2) SME-enabled node with memory encryption, without file encryption (SME-M⊕F⊖); 3) SME-enabled node with … view at source ↗
read the original abstract

Traditionally, the architecture of high-performance computing (HPC) systems is tailored for speed, while highly secure computer systems must sacrifice speed for security. However, a wide range of scientific domains, such as the life sciences, call for a combination of performance and security to allow processing sensitive data at scale. Here, we present RAMSES (Research Accelerator for Modeling and Simulation with Enhanced Security), an HPC system designed from the ground up to deliver high performance within a robust security framework. RAMSES integrates hardware-based memory encryption of AMD processors with state-of-the-art file encryption from IBM Storage Scale and the Thales CipherTrust manager, establishing an HPC platform that ensures continuous encryption throughout the data life cycle - at rest, in transit, and in use - in compliance with major data protection standards (European General Data Protection Regulation, ISO/IEC 27001 certification, and Federal Information Processing Standards). In addition, we implemented advanced operating system hardening, a multi-layered security architecture, and mandatory multi-factor authentication to adapt the HPC environment to increased security demands. Benchmark results from the biomedical sector demonstrate that the performance impact of the secure environment is limited and that integration of the conflicting requirements speed and security can be achieved while preserving a coherent, flexible, and user-friendly system.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript describes RAMSES, an HPC system integrating AMD SME hardware memory encryption, IBM Storage Scale file encryption, Thales CipherTrust key management, OS hardening, multi-layered security architecture, and mandatory MFA. The design targets continuous encryption (at rest, in transit, and in use) for sensitive biomedical data while complying with GDPR, ISO/IEC 27001, and FIPS. The central claim is that biomedical-sector benchmarks demonstrate limited performance impact, showing that speed and security requirements can be reconciled in a coherent, flexible, user-friendly system.

Significance. If the performance claims are substantiated with quantified overheads against unsecured baselines and representative HPC workloads, the work would be significant for domains requiring secure processing of sensitive data at scale. The explicit end-to-end encryption stack and compliance mapping constitute a concrete systems contribution that could serve as a reference for other secure HPC deployments.

major comments (2)
  1. [Abstract] Abstract: The load-bearing claim that 'benchmark results from the biomedical sector demonstrate that the performance impact of the secure environment is limited' supplies no quantitative overhead figures, workload descriptions, comparison baselines, error bars, or statistical details. Without these, the central performance claim cannot be evaluated.
  2. [Abstract] Abstract: The assumption that the encryption stack (AMD SME + IBM Storage Scale + Thales CipherTrust) plus OS hardening will continue to deliver acceptable performance under production workloads beyond the specific biomedical benchmarks is untested in the provided text; no additional access patterns or scaling results are referenced to support generalizability.
minor comments (1)
  1. The abstract would be strengthened by including at least one concrete performance metric (e.g., percentage overhead on a named benchmark) to allow readers to assess the 'limited impact' claim immediately.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback on our manuscript. We address the major comments point by point below, agreeing where revisions are needed to improve clarity and substantiation of claims.

read point-by-point responses
  1. Referee: [Abstract] Abstract: The load-bearing claim that 'benchmark results from the biomedical sector demonstrate that the performance impact of the secure environment is limited' supplies no quantitative overhead figures, workload descriptions, comparison baselines, error bars, or statistical details. Without these, the central performance claim cannot be evaluated.

    Authors: We agree that the abstract lacks the requested quantitative details. The full manuscript (Section 4) contains the benchmark results with overhead figures, workload descriptions (e.g., representative biomedical applications), comparison baselines (unsecured vs. secured configurations), error bars, and statistical details. We will revise the abstract to include key quantitative results summarizing these findings. revision: yes

  2. Referee: [Abstract] Abstract: The assumption that the encryption stack (AMD SME + IBM Storage Scale + Thales CipherTrust) plus OS hardening will continue to deliver acceptable performance under production workloads beyond the specific biomedical benchmarks is untested in the provided text; no additional access patterns or scaling results are referenced to support generalizability.

    Authors: The manuscript scope is centered on the biomedical sector with benchmarks for workloads typical of that domain. We do not present additional access patterns or scaling results beyond these, nor do we claim broad generalizability. We will revise the abstract and/or discussion section to explicitly note this scope limitation and indicate that further validation for other workloads would be required. revision: partial

Circularity Check

0 steps flagged

No circularity: systems description with external benchmarks, no derivations or self-referential predictions

full rationale

The paper describes an HPC system implementation (AMD SME + IBM Storage Scale + Thales CipherTrust + OS hardening) and cites benchmark results from the biomedical sector to support performance claims. No equations, fitted parameters, predictions, or derivation chains exist. Claims rest on implementation details and external benchmarks rather than reducing to self-definitions or self-citations. No load-bearing steps match any enumerated circularity pattern.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

This is a systems-engineering report on a deployed platform. No mathematical derivations, fitted constants, or new theoretical entities are involved; the central claim rests entirely on the described implementation and the (undetailed) benchmark results.

pith-pipeline@v0.9.1-grok · 5780 in / 1102 out tokens · 39598 ms · 2026-06-29T02:43:10.383212+00:00 · methodology

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