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arxiv 2009.05230 v1 pith:UHPETGHJ submitted 2020-09-11 cs.AR cs.DC

Accelerating Recommender Systems via Hardware "scale-in"

classification cs.AR cs.DC
keywords hardwarearchitectureimpactinterconnectlargememoryprocessorsrecommender
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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In today's era of "scale-out", this paper makes the case that a specialized hardware architecture based on "scale-in"--placing as many specialized processors as possible along with their memory systems and interconnect links within one or two boards in a rack--would offer the potential to boost large recommender system throughput by 12-62x for inference and 12-45x for training compared to the DGX-2 state-of-the-art AI platform, while minimizing the performance impact of distributing large models across multiple processors. By analyzing Facebook's representative model--Deep Learning Recommendation Model (DLRM)--from a hardware architecture perspective, we quantify the impact on throughput of hardware parameters such as memory system design, collective communications latency and bandwidth, and interconnect topology. By focusing on conditions that stress hardware, our analysis reveals limitations of existing AI accelerators and hardware platforms.

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