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REVIEW 4 major objections 6 minor 39 references

Hierarchical Recursive Precision for Accelerating Symmetric Linear Solves on MXUs

T0 review · 4 major / 6 minor · reviewed 2026-08-03 · deepseek-v4-flash

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Pith's one-line read A fully nested recursive Cholesky factorization can assign low-precision FP16 arithmetic to large off-diagonal blocks while keeping diagonal blocks in higher precision, yielding multi-fold speedups on AI-specialized GPUs without sacrificing

desk verdict Plausible speedups and a useful portable design, but the stability claim is narrower than advertised and the evidence needs an artifact release. read the letter →

arxiv 2601.08082 v3 pith:Y2JTYCTI submitted 2026-01-12 cs.DC cs.ETcs.MScs.PF

Vicki Carrica , Rabab Alomairy , Evelyne Ringoot , Alan Edelman This is my paper
classification cs.DCcs.ETcs.MScs.PF MSC 65F0565Y05
keywords CholeskyfactorizationmixedprecisionrecursivesubdivisionFP16arithmeticGPUaccelerationtensorcoressymmetricpositivedefinitesystemsportableJuliasolver
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that a fully nested recursive Cholesky factorization can safely assign low-precision (FP16) arithmetic to large off-diagonal blocks while keeping high precision on diagonal blocks, giving multi-fold speedups on AI-specialized GPU hardware without losing the accuracy needed for scientific computing. The authors present a portable Julia solver that recursively subdivides all three phases — the diagonal factorization, triangular solve, and rank-k update — and layers precision by recursion depth. On a large (n=65,536) diagonally dominant symmetric positive-definite system, the deepest configuration runs about 5.3 times faster than the vendor double-precision solver while preserving 5–6 correct digits, roughly 100 times better accuracy than using half precision everywhere. The same algorithm runs on both NVIDIA and AMD GPUs, suggesting the approach generalizes beyond any one vendor. If valid, this gives scientists a practical way to use tensor-core accelerators for problems that previously required double precision.

What carries the argument

The recursive decomposition tree: at each level the matrix is split into a diagonal block and a trailing submatrix, and all three core operations — diagonal factorization (POTRF), triangular solve (TRSM), and symmetric rank-k update (SYRK) — are applied recursively rather than in standard blocked form. This tree is the data structure that carries the mixed-precision hierarchy: precision is assigned per recursion level, with large off-diagonal blocks handled by FP16 GEMM and diagonal blocks by FP32/FP64. A per-block quantization step rescales blocks into FP16's representable range before low-precision operations and rescales them back afterward, which the paper argues is necessary and cheap.

What would settle it

Measure the factorization error ||A - LL^T||/||A|| for the deepest FP16 configuration on a dense SPD matrix with condition number 10^6 and n=65,536; the paper predicts roughly 5–6 digits, while pure FP16 gives below 4. If the measured error matches pure FP16 (below 4 digits), the claimed accuracy benefit is falsified. Alternatively, a single run on a matrix with dynamic range above 1e11 (e.g., raefsky4) producing NaN would show the static scaling assumption fails.

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Extended reading notes

Core claim

The central discovery is that the numerical sensitivity of Cholesky factorization is concentrated near the diagonal for diagonally dominant SPD matrices, so the abundant off-diagonal GEMM work can be executed in FP16 without destroying stability, provided diagonal blocks are computed in higher precision and each low-precision block is rescaled to FP16's range. The paper implements this as a recursive tree that splits the matrix at each level into two recursive factorizations, one triangular solve, and one symmetric rank-k update, assigning lower precision to blocks further from the diagonal. The claimed payoff is quantitative: up to 5.32x speedup over the vendor FP64 baseline on H200 with 5–

Load-bearing premise

For diagonally dominant SPD matrices, the off-diagonal blocks are insensitive enough that static FP16 scaling does not destroy the factorization, and this holds as recursion depth increases.

Editorial extensions

If this is right

  • Large diagonally dominant SPD systems can be solved several times faster than double-precision vendor libraries on existing tensor-core hardware.
  • Recursive SYRK and fully nested recursive mixed-precision Cholesky are feasible on both NVIDIA and AMD GPUs from a single portable implementation.
  • Accuracy can be traded continuously with speed by choosing recursion depth and precision layering (e.g., a configuration with a top FP64 layer yields roughly 9 digits at 1.21x speedup, while deeper FP16 layers yield 5–6 digits at 5.32x speedup).
  • The approach is least effective for small matrices (n < 16,000) and fails for matrices with extreme dynamic range, where static blockwise quantization causes underflow and NaN propagation.
  • Peak utilization is not the right objective: layered mixed precision can trade a modest loss of raw throughput for dramatically improved accuracy while still delivering multi-fold speedup over high-precision solvers.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same tree-structured precision hierarchy could extend to LDL^T factorizations and indefinite systems, where diagonal pivoting complicates precision assignment but the off-diagonal insensitivity argument may partially carry over.
  • Because accuracy is measured as factorization error rather than solve residual, the 5–6 digit claim may be conservative for well-conditioned right-hand sides; combining this solver with iterative refinement could recover full precision at modest extra cost, making the speedup usable in production.
  • The static blockwise scaling is the clearest extension point: adaptive or per-block dynamic scaling based on block norms or exponent ranges might extend the method to matrices like raefsky4 without losing the performance advantage.
  • Performance portability across AMD and NVIDIA depends on the availability of mixed-precision GEMM; once AMD's mixed-precision GEMM matures, the AMD speedups may approach the NVIDIA numbers.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. The paper proposes a nested recursive Cholesky factorization for symmetric positive-definite systems, in which not only POTRF but also TRSM and SYRK are recursively subdivided. A layered mixed-precision scheme assigns FP16 to large off-diagonal blocks and higher precision (FP32/FP64) to diagonal blocks, with per-block quantization to mitigate FP16 dynamic-range issues. The implementation is in Julia and is evaluated on NVIDIA H200 and AMD MI300X. The central quantitative claim is up to a 5.32x speedup over cuSOLVER FP64 at n=65,536 while retaining 5-6 digits of factorization accuracy, about 100x better than pure FP16. The paper also claims the first recursive GPU SYRK and cross-vendor portability.

Significance. If the numerical and performance claims hold, the work is a useful contribution: it combines recursive blocking with tensor-core/matrix-core low-precision arithmetic in a portable way, and it addresses a real bottleneck in symmetric direct solvers. The Julia multiple-dispatch design is a credible route to hardware-agnostic mixed-precision linear algebra. The authors are transparent about several limitations (small matrices, dynamic-range sensitivity, AMD missing mixed-precision GEMM), which increases confidence in the reported experiments. However, the central numerical-stability premise is not proven for the stated target class, and the performance results are not accompanied by code, data, or error bars, so reproduction is not currently possible.

major comments (4)
  1. [§3.2, §4.1–4.2, §4.5] The numerical-stability premise is load-bearing but unproven. §3.2 asserts that for diagonally dominant matrices 'the most numerically sensitive operations' are near the diagonal, but the benchmarks use A = rand(n) + nI, which has condition number near 1, and one moderately conditioned real matrix (bodyy5). A strictly diagonally dominant SPD matrix with O(1) entries can have condition growing with n (e.g., the 2D Laplacian); FP16 off-diagonal rounding (~1e-3 relative) may then be amplified through the Schur complement, and the claimed 5–6 digits of accuracy are not established. The failure reported for raefsky4 in §4.5 is attributed to dynamic range, but dynamic range is not the only possible failure mode. Without an error bound or experiments on diagonally dominant matrices with growing condition number, the headline accuracy claim is unsupported for the stated target class.
  2. [Figures 4–12; §4.1] The performance claims are not reproducible from the manuscript: no code, no data, no per-run statistics, and no error bars are provided. The vendor baselines (cuSOLVER FP64/FP32, rocSOLVER FP64) and any tuning parameters for the recursive kernels or leaf block sizes are not described in enough detail for an independent implementation. For a systems/performance paper, this is a major gap: the central speedup figures cannot currently be verified.
  3. [§4.6, Figure 12] The cross-platform comparison is not apples-to-apples. The text states that mixed-precision GEMM (GemmEx) was included for NVIDIA but not for AMD because of availability in the Julia ecosystem. Thus the lower MI300X speedups and the portability claim in Figure 12 conflate algorithmic portability with the absence of an available vendor path on one platform. The claim of 'similar gains' on AMD is therefore weaker than the NVIDIA results.
  4. [Abstract and §4.2] The headline performance number is reported inconsistently. The abstract says '5.07x speedup relative to the diagonal-precision vendor baseline' (presumably 'double-precision'), while §4.2 and the introduction report 5.32x versus cuSOLVER FP64. The deepest mixed-precision configuration is also written with different numbers of FP16 layers in the same section: [F16,F16,F16,F16,F16,F32], [F16,F16,F16,F16,F16,F16,F32], and [F16,F16,F16,F16,F16,F16,F16,F32] are all mentioned. This ambiguity needs to be resolved because the 5.32x claim is the central result.
minor comments (6)
  1. [Abstract] 'diagonal-precision' appears to be a typo for 'double-precision'; please correct.
  2. [§3.3] The scaling formula defines alpha but does not explicitly state that B_alg is set to B/alpha before the low-precision operation and that the output is multiplied by alpha; make this two-step explicit.
  3. [§2.1] The claim of 'first recursive GPU-based SYRK' would be easier to evaluate if the related-work search were explicit; currently no comparison to any prior recursive SYRK implementation is provided.
  4. [§4.5] The text refers to Figure 11 when discussing small-matrix overhead, but Figure 11 is a scaling plot; consider referencing a more appropriate figure or clarifying the intended comparison.
  5. [Figure 8] The y-axis label '-log10 relative error' can be misread as 'digits of accuracy'. Define the relationship explicitly.
  6. [Algorithm 1] The partition uses A21 in the split but the algorithm description says lower Cholesky; check that the transpose notation is consistent with a lower-triangular factor.

Circularity Check

0 steps flagged · score 1.0 of 10

No significant circularity; empirical benchmarks and accuracy comparisons are self-contained.

full rationale

The paper's central claims are quantitative benchmark results: mixed-precision recursive Cholesky configurations achieve up to 5.32x speedup over cuSOLVER FP64 with 5-6 digits of factorization accuracy. These numbers are measured against external vendor baselines (cuSOLVER/rocSOLVER) and an independent FP64 factorization residual, not derived from the method's own assumptions. There is no fitted parameter that is subsequently renamed as a prediction, and no equation in Sections 3.1-3.3 defines the claimed accuracy or speedup in terms of the inputs. The quantization/quantization scheme is a deterministic scaling operation, not a model fit. The numerical-sensitivity assumption for diagonally dominant matrices is stated qualitatively in Section 3.2 and is not proven, but an unproven assumption is a correctness/stability risk, not circularity. The paper explicitly documents the failure on Simon/raefsky4, so it does not hide its limitation. The only self-citations ([16], [17]) refer to the authors' earlier recursive TRSM work and a poster; these are used as background and as evidence of portable Julia GPU kernels, but the current paper's own benchmarks and external baselines carry the central argument. No uniqueness theorem or imported ansatz is invoked to force the mixed-precision hierarchy. Therefore no circular step can be exhibited with a specific reduction, and the appropriate finding is no significant circularity, with a minor non-load-bearing self-citation noted.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

The central empirical result rests on two hand-tuned choices (leaf size, precision hierarchy) and on the domain assumption that diagonally dominant SPD matrices tolerate FP16 in off-diagonal blocks. No new physical entities are introduced.

free parameters (3)
  • leaf block size b = not reported
    Leaf size controls when recursion bottoms out into vendor kernels; it is tuned per hardware and not stated in the paper.
  • precision hierarchy configuration = various, e.g. [F16,F16,F16,F16,F16,F16,F32]
    The paper sweeps precision assignments and reports the best; the chosen hierarchy is selected to maximize speedup at acceptable accuracy.
  • diagonal shift n for synthetic matrices = n (matrix size)
    Synthetic SPD matrices are generated as uniform random entries plus n on the diagonal; this guarantees strong diagonal dominance and favorable conditioning, which may not reflect real-world matrices.
assumptions (4)
  • standard math Recursive block decomposition of an SPD matrix into diagonal and off-diagonal blocks yields the same Cholesky factors as the standard algorithm.
    Invoked in Algorithms 1-3; correctness of recursive Cholesky is established in the literature (e.g., Andersen et al.).
  • domain assumption Off-diagonal blocks are numerically less sensitive than diagonal blocks for diagonally dominant SPD matrices, so FP16 round-off there is acceptable.
    Section 3.2 states this as the motivation for the precision hierarchy; no error analysis is provided.
  • domain assumption Static per-block quantization scaling alpha keeps values in FP16 range without materially changing the result for matrices of limited dynamic range.
    Section 3.3 defines the scaling; the paper later shows it fails when dynamic range exceeds ~1e11 (Section 4.5).
  • domain assumption Vendor BLAS/LAPACK kernels (POTRF, TRSM, SYRK, GEMM) used for base cases meet the expected accuracy and performance on both H200 and MI300X.
    The solver dispatches base cases to cuBLAS/cuSOLVER/rocBLAS/rocSOLVER; their FP16 implementations are assumed stable enough for off-diagonal work.

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Cite this review

Pith. "Pith review of Hierarchical Recursive Precision for Accelerating Symmetric Linear Solves on MXUs." pith.science (2026). https://pith.science/paper/Y2JTYCTI

@misc{pith2026260108082,
  author       = {Pith},
  title        = {Pith review of: Hierarchical Recursive Precision for Accelerating Symmetric Linear Solves on MXUs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/Y2JTYCTI}},
  note         = {Machine review of arXiv:2601.08082}
}
read the original abstract

Symmetric positive-definite system solvers based on Cholesky factorization are fundamental to many scientific applications, such as climate modeling. We present a portable, nested recursive mixed-precision solver designed for Matrix Processing Units (MXUs), including NVIDIA Tensor Cores (H200) and AMD Matrix Cores (MI300X), that assigns low-precision FP16 arithmetic to large off-diagonal blocks, while preserving high precision on diagonal blocks to ensure numerical stability. The solver is implemented in Julia, providing a high-level, hardware-agnostic interface. We demonstrate up to a 5.07x speedup relative to the diagonal-precision vendor baseline, with 100x better accuracy than pure half precision on H200, providing higher accuracy than low-precision at higher speed than high-precision. Positive performance trends are also observed on MI300X, demonstrating broad applicability across GPUs.

Figures

Figures reproduced from arXiv: 2601.08082 by the authors.

Figure 1
Figure 1. Nested Recursive Cholesky Decomposition Tree Specifically, we assign: (i) Low precision (e.g., FP16) to large, off-diagonal blocks that dominate the computation but are less sensitive to numerical error. These are typically updated using GEMM during TRSM and SYRK phases. (ii) Higher precision (e.g., FP32 or FP64) to diagonal blocks, which undergo POTRF and are more susceptible to round-off errors. These blocks contr… view at source ↗
Figure 2
Figure 2. Recursive data structure enabling layered mixed precision [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 4
Figure 4. Speedup of Recursive SYRK on NVIDIA H200. Relative performance of the recursive Symmetric Rank-k update compared to cuBLAS FP64 [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗
Figures from the paper (5 more)
Figure 6
Figure 6. Figure 6: Cholesky Throughput on NVIDIA H200. Effective TFLOPs across matrix sizes. slightly exceed the cuSOLVER FP64 throughput. The triple-precision [F16, F32, F64] configuration provides an intermediate boost, reaching roughly 54 TFLOP/s. Meanwhile, the deep mixed-precision c…
Figure 8
Figure 8. Figure 8: Cholesky Accuracy on NVIDIA H200. Relative error norms (− log10) for various precision configurations. 4.3 Results Analysis on AMD MI300X [PITH_FULL_IMAGE:figures/full_fig_p009_8.png]
Figure 9
Figure 9. Figure 9: Cholesky Speedup on AMD MI300X. Performance compared to ROCSOLVER FP64. We evaluate our recursive Cholesky solver on the AMD MI300X, us￾ing vendor-optimized rocSOLVER FP64 as the baseline [PITH_FULL_IMAGE:figures/full_fig_p010_9.png]
Figure 10
Figure 10. Figure 10: Performance and accuracy of mixed-precision configurations on the bodyy5 matrix on NVIDIA H200 GPU. Runtime (left) and relative error (right) demonstrate that mixed-precision configurations achieve substantial speedups while maintaining numerical stability. bodyy5. Ou…
Figure 11
Figure 11. Figure 11: Speedup Scaling with Ma￾trix Size on NVIDIA hardware. Performance gains improve sub￾stantially as the matrix grows, al￾lowing for deeper recursion levels [PITH_FULL_IMAGE:figures/full_fig_p012_11.png]

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