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Paper Citation Record · LEDGER

LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

As of 14 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 10 inbound Pith citation observations for arXiv:2406.17132.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2406.17132 v2

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 10 of 10 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-14T06:32:32.682623+00:00

measured 10 of 10 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-12T21:36:11.949534Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-07-01T14:05:46.824011Z

Reference resolution

0 of 0 outbound references displayed

  • verified exact0
  • verified fuzzy0
  • unresolved0
  • parse uncertain0
  • malformed identifier0
  • metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 724a5186-1588-48ae-beb1-61a516e050b9 · inbound

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design cites this paper.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

Reference 14

Resolution
unresolved
no resolver link, observed 2026-08-12T21:36:11.949534Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-12T21:36:11.949534Z digest=sha256:8ed7b8ef1d1f198ac952a89fdb6e9c6fccfae2650024b2e63f5a761a725988da

Observation d38eec10-bb21-4cc7-8233-9983ac59a6bc · inbound

Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI cites this paper.

Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

Reference 8

Resolution
unresolved
no resolver link, observed 2026-08-12T15:23:21.436548Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-12T15:23:21.436548Z digest=sha256:fde635a6e8464eb7f70738d22ea7c5b55a42a266720e90264c47fad142c4efa2

Observation 2ec34ea9-f22a-4aac-a8a1-554d7437f643 · inbound

RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation cites this paper.

RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

Reference 10

Resolution
unresolved
no resolver link, observed 2026-08-12T12:02:46.909199Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-12T12:02:46.909199Z digest=sha256:5a68a19d896564b50bb25dbd8122e5990514f707807e2fd5d802fdb91645c4bd

Observation 721305d4-1a1f-4777-8e29-3e099e55de48 · inbound

ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning cites this paper.

ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

Reference 27

Resolution
verified exact
arxiv_id, observed 2026-05-19T06:52:08.368301Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

source=pdf_text observed=2026-05-19T06:48:29.015759Z digest=sha256:00dbc1f9b1c31895c076a73cd0849a8fd5bcd327e469190ea7fe869a57ce541f

Observation 0b11534d-22e5-4a7a-89c3-bca91aa9b440 · inbound

UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification cites this paper.

UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

Reference 5

Resolution
verified exact
arxiv_id, observed 2026-05-11T18:31:13.621435Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

source=pdf_text observed=2026-05-08T15:36:38.153161Z digest=sha256:54e4b7ec75b3f38b8cfd33c9334a95b5e25823145d29410b680e8380e687ddb6

Observation ec585513-5a6a-4b36-b927-80f24d2d1875 · inbound

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges cites this paper.

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

Reference 24

Resolution
verified exact
arxiv_id, observed 2026-05-12T06:51:26.508712Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

source=pdf_text observed=2026-05-12T03:57:51.577486Z digest=sha256:de2dc7f2c1fdf8710cff9e74117f7dbd694bec6d5771ef43681070492900ad04

Observation 935fa800-ff2b-4a4f-9745-3acc16a11eda · inbound

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges cites this paper.

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

Reference 25

Resolution
verified exact
arxiv_id, observed 2026-05-14T21:12:58.767088Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

source=pdf_text observed=2026-05-14T21:12:08.821202Z digest=sha256:b9e3bdd5385369fe14038a16d68ed590e80d591a4859f03013e3a0259bab2fe2

Observation 36a05fba-bf8d-420f-be7d-e43811665047 · inbound

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges cites this paper.

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

Reference 25

Resolution
verified exact
arxiv_id, observed 2026-05-21T08:59:55.416926Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

source=pdf_text observed=2026-05-21T08:58:25.469021Z digest=sha256:8621fc4738b2272929c0ef2f642fd5c93a3c3278f42557ac4ff8c4ac57285d10

Observation 953e7c8b-06c7-4e47-8932-8f75af29d43f · inbound

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges cites this paper.

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

Reference 25

Resolution
verified exact
arxiv_id, observed 2026-07-01T14:05:46.825382Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

source=pdf_text observed=2026-06-30T22:18:09.663488Z digest=sha256:9ad2ea45a9fa9bc1d5c2d97a080895ee5b0fdcd5f1647f565127e9587121675a

Observation 4c21de54-efd4-44e0-815b-302a87e7ace9 · inbound

Hardware Design and Security in the Era of Chiplets and LLMs cites this paper.

Hardware Design and Security in the Era of Chiplets and LLMs LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

Reference 33

Resolution
unresolved
no resolver link, observed 2026-08-06T10:13:18.606997Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T10:13:18.606997Z digest=sha256:6a4023685c0f5d546e3d5759637ec66e7e888b4f5a2e350306eb1f41b3a40186