A compiler for neutral-atom NISQ devices introduces hub traps and shuttling rules to compile circuits that SWAP-only methods cannot handle in practical time, eliminating SWAP gates and improving a fidelity proxy on routing-dominated benchmarks.
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Lightsabre: A lightweight and enhanced sabre algorithm
13 Pith papers cite this work. Polarity classification is still indexing.
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QAP-Router models qubit routing as dynamic QAP and applies RL with a solution-aware Transformer to cut CNOT counts by 12-30% versus industry compilers on real circuit benchmarks.
dSABRE cuts geometric-mean EPR consumption by 41-44% versus TeleSABRE on 18 benchmark circuits through intra-core priority, a five-term teleportation scorer with capacity penalty, proactive congestion relief, and BFS-layer extended sets.
A co-design method for frequency allocation and noise-aware transpilation in tunable-coupler quantum systems yields 8.9% lower log-infidelity cost and 6.8% shorter circuits than SABRE on SNAIL architectures.
Reinforcement learning policy for qubit mapping reduces SWAP overhead by 65-85% versus standard quantum compilers on MQTBench and Queko benchmark circuits.
Digital Annealer-assisted transpilation reduces CNOT counts by 13.7% on average (up to 57.4%) versus Qiskit on structured circuits, with a full-DA variant outperforming ISAAQ by 23.1%.
Position graph abstraction with memoized SABRE heuristics scales qubit mapping and routing for TI-QCCD architectures by caching repeated evaluations without altering decisions.
Noise-aware selection of circuit cutting strategies reduces execution overhead by 5-54x for 20-qubit circuits and makes 50-qubit circuit cutting feasible on non-uniformly noisy hardware.
SimpleTES scales test-time evaluation in LLMs to discover state-of-the-art solutions on 21 scientific problems across six domains, outperforming frontier models and optimization pipelines with examples like 2x faster LASSO and new Erdos constructions.
AlphaCNOT combines reinforcement learning with Monte Carlo Tree Search planning to reduce CNOT gate counts by up to 32% versus heuristics in quantum circuit synthesis.
Canopus unifies qubit mapping and routing across quantum ISAs by modeling synthesis costs via canonical two-qubit gate forms, achieving 15-35% lower routing overhead than prior methods on varied backends and topologies.
TeleSABRE extends SABRE to combine intra-core SWAPs with inter-core teleportation, reporting a 28% reduction in inter-core operations on benchmarks for multi-core quantum architectures.
Hardware transpilation of parameterized quantum circuits produces ansatz-dependent shifts in expressibility (up to 125%) and trainability (up to 25%), altering the expected trade-off between them.
citing papers explorer
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A Neutral-Atom Quantum Compiler with Application-Specific Layout and Hub-Assisted Shuttling
A compiler for neutral-atom NISQ devices introduces hub traps and shuttling rules to compile circuits that SWAP-only methods cannot handle in practical time, eliminating SWAP gates and improving a fidelity proxy on routing-dominated benchmarks.
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QAP-Router: Tackling Qubit Routing as Dynamic Quadratic Assignment with Reinforcement Learning
QAP-Router models qubit routing as dynamic QAP and applies RL with a solution-aware Transformer to cut CNOT counts by 12-30% versus industry compilers on real circuit benchmarks.
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dSABRE: A SABRE-Style Router for Multi-Core Distributed Quantum Computers
dSABRE cuts geometric-mean EPR consumption by 41-44% versus TeleSABRE on 18 benchmark circuits through intra-core priority, a five-term teleportation scorer with capacity penalty, proactive congestion relief, and BFS-layer extended sets.
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Fidelity-Aware Frequency Allocation and Transpilation Co-Design for Tunable Coupler Quantum Systems
A co-design method for frequency allocation and noise-aware transpilation in tunable-coupler quantum systems yields 8.9% lower log-infidelity cost and 6.8% shorter circuits than SABRE on SNAIL architectures.
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CO-MAP: A Reinforcement Learning Approach to the Qubit Allocation Problem
Reinforcement learning policy for qubit mapping reduces SWAP overhead by 65-85% versus standard quantum compilers on MQTBench and Queko benchmark circuits.
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Digital Annealer-Assisted Accuracy-First Quantum Circuit Transpilation with Integrated QUBO Mapping and Routing
Digital Annealer-assisted transpilation reduces CNOT counts by 13.7% on average (up to 57.4%) versus Qiskit on structured circuits, with a full-DA variant outperforming ISAAQ by 23.1%.
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Scaling Qubit Mapping and Routing With Position Graph Abstraction and Memoization
Position graph abstraction with memoized SABRE heuristics scales qubit mapping and routing for TI-QCCD architectures by caching repeated evaluations without altering decisions.
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Noise-aware selection of circuit cutting strategies under hardware noise non-uniformity
Noise-aware selection of circuit cutting strategies reduces execution overhead by 5-54x for 20-qubit circuits and makes 50-qubit circuit cutting feasible on non-uniformly noisy hardware.
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Evaluation-driven Scaling for Scientific Discovery
SimpleTES scales test-time evaluation in LLMs to discover state-of-the-art solutions on 21 scientific problems across six domains, outperforming frontier models and optimization pipelines with examples like 2x faster LASSO and new Erdos constructions.
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AlphaCNOT: Learning CNOT Minimization with Model-Based Planning
AlphaCNOT combines reinforcement learning with Monte Carlo Tree Search planning to reduce CNOT gate counts by up to 32% versus heuristics in quantum circuit synthesis.
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Unifying Qubit Routing Across Diverse Quantum ISAs via Canonical Representation
Canopus unifies qubit mapping and routing across quantum ISAs by modeling synthesis costs via canonical two-qubit gate forms, achieving 15-35% lower routing overhead than prior methods on varied backends and topologies.
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TeleSABRE: Layout Synthesis in Multi-Core Quantum Systems with Teleport Interconnect
TeleSABRE extends SABRE to combine intra-core SWAPs with inter-core teleportation, reporting a 28% reduction in inter-core operations on benchmarks for multi-core quantum architectures.
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Beyond Logical Circuits: Hardware-Aware Analysis of Expressibility and Trainability in Variational Quantum Algorithms
Hardware transpilation of parameterized quantum circuits produces ansatz-dependent shifts in expressibility (up to 125%) and trainability (up to 25%), altering the expected trade-off between them.