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The Processing Using Memory Paradigm:In-DRAM Bulk Copy, Initialization, Bitwise AND and OR
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In existing systems, the off-chip memory interface allows the memory controller to perform only read or write operations. Therefore, to perform any operation, the processor must first read the source data and then write the result back to memory after performing the operation. This approach consumes high latency, bandwidth, and energy for operations that work on a large amount of data. Several works have proposed techniques to process data near memory by adding a small amount of compute logic closer to the main memory chips. In this article, we describe two techniques proposed by recent works that take this approach of processing in memory further by exploiting the underlying operation of the main memory technology to perform more complex tasks. First, we describe RowClone, a mechanism that exploits DRAM technology to perform bulk copy and initialization operations completely inside main memory. We then describe a complementary work that uses DRAM to perform bulk bitwise AND and OR operations inside main memory. These two techniques significantly improve the performance and energy efficiency of the respective operations.
Forward citations
Cited by 6 Pith papers
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PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems
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HE-PIM: Demystifying Homomorphic Operations on a Real-world Processing-in-Memory System
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PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips
Multiple-row activation used by processing-using-DRAM triggers read-disturbance bit flips with as few as 26 row activations, up to 158x fewer than RowHammer, and can bypass in-DRAM Target Row Refresh protections.
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Towards Efficient LUT-based PIM: A Scalable and Low-Power Approach for Modern Workloads
A DRAM LUT-based computing scheme uses one row activation per scalar-vector batch and per-mat independent column reads to cut activation energy, plus an HBM accelerator that counts quantized exponents for transformer ...
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Memory-Centric Computing: Security Benefits and Challenges of Processing-in-DRAM
Processing-in-DRAM enables new DRAM-based TRNGs (16.05 Gb/s) and PUFs (5.75% lower latency) on real chips but increases read disturbance by 158x and creates 14.8 Mb/s timing channels.
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