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arxiv: 2606.20786 · v1 · pith:4DAWPNDHnew · submitted 2026-06-18 · 💻 cs.CR · cs.AR· cs.DC

Memory-Centric Computing: Security Benefits and Challenges of Processing-in-DRAM

Ismail Emir Yuksel , F. Nisa Bostanci , Ataberk Olgun , Onur Mutlu This is my paper

Pith reviewed 2026-06-26 16:45 UTC · model grok-4.3

classification 💻 cs.CR cs.ARcs.DC
keywords processing-in-DRAMmemory-centric computingtrue random number generatorphysical unclonable functionread disturbancetiming channelDRAM security
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The pith

Processing-in-DRAM turns memory into an active substrate that supplies new security primitives while creating fresh attack surfaces.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper argues that shifting computation into DRAM reduces data movement and enables in-memory security features such as true random number generators and physical unclonable functions. It shows these features can reach high throughput and low latency on real chips. At the same time the same substrate change amplifies existing DRAM vulnerabilities, making read-disturbance attacks easier and creating new high-bandwidth timing channels. A sympathetic reader would care because future systems that move work to memory will inherit both the protective and the exposing effects. The authors conclude that DRAM should be designed from the start as a joint computation, storage, and security substrate.

Core claim

Processing-in-DRAM exploits and enhances the operational characteristics of real DRAM chips to perform computation on stored data, yielding new state-of-the-art true random number generators with up to 16.05 Gb/s throughput and physical unclonable functions with 5.75 percent lower evaluation latency than prior work, while simultaneously amplifying DRAM read disturbance by a factor of 158 in the minimum number of accesses needed to induce the first bitflip and enabling memory timing channels with 14.8 Mb/s throughput.

What carries the argument

Processing-in-DRAM (PiD), the exploitation and enhancement of DRAM operational characteristics to perform computation directly on data stored in the DRAM array.

If this is right

  • DRAM can now serve as a source of high-throughput true random numbers without moving data off the chip.
  • Physical unclonable functions can be realized with lower evaluation latency than previous DRAM-based designs.
  • Rowhammer-style read-disturbance attacks become feasible with far fewer accesses once computation is performed in DRAM.
  • Memory timing channels can reach communication rates of 14.8 Mb/s when computation occurs inside the DRAM array.
  • Future DRAM designs must treat computational capability, storage density, and security as co-equal goals.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same substrate changes may affect security in other processing-in-memory technologies that move work closer to data.
  • System software and hardware architects will need new mechanisms to isolate computation inside memory from untrusted code.
  • Security evaluations of future memory chips will have to account for both the new primitives and the new disturbance surfaces simultaneously.

Load-bearing premise

The measured security benefits and challenges arise directly from the way DRAM chips can be made to compute on their own stored data.

What would settle it

Real DRAM chips that, when configured for in-DRAM computation, fail to produce the reported 16.05 Gb/s TRNG throughput or the 158x reduction in accesses required for the first bitflip.

Figures

Figures reproduced from arXiv: 2606.20786 by Ataberk Olgun, F. Nisa Bostanci, Ismail Emir Yuksel, Onur Mutlu.

Figure 3
Figure 3. Figure 3: Throughput of generating true random numbers [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 2
Figure 2. Figure 2: Average 512-bit cache-block entropy for varying num [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 4
Figure 4. Figure 4: Inter- (orange) and intra-Jaccard (blue) indices ob [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Distribution of the change in HCf irst change with double-sided SiMRA compared to double-sided RowHammer (left) and the lowest HCf irst observed with double-sided SiMRA and RowHammer (right). across 60 five-core multiprogrammed workloads, showing that extending existing RowHammer defenses to PuD is costly and that read-disturbance-resilient PuD systems call for new solu￾tions. 3.2. Timing Attacks in Proces… view at source ↗
Figure 6
Figure 6. Figure 6: PuM covert-channel attack flow (IMPACT-PuM). [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
read the original abstract

Today's computing systems are processor-centric: they require frequent data movement between processing elements (e.g., CPU) and main memory (DRAM), leading to significant inefficiencies in performance and energy consumption. Memory-centric computing instead moves computation to the data, enabling computation capability in and near all places where data is generated and stored, and greatly reducing the performance and energy overheads of data access and data movement. This shift from a processor-centric to a memory-centric paradigm has important and underexplored consequences for system security. Turning memory from a dumb, inactive store into an active computing substrate introduces benefits as well as challenges for system security: it can provide new in-memory security primitives and also reduce data exposure, but it can also expose new attack surfaces. This work discusses the security benefits and challenges of memory-centric computing, specifically Processing-in-DRAM (PiD), a paradigm where the operational characteristics of a DRAM chip are exploited and enhanced to perform computation on data stored in DRAM. Specifically, we describe 1) new state-of-the-art DRAM-based true random number generators that provide up to 16.05 Gb/s throughput and physical unclonable functions with 5.75% lower evaluation latency than the prior state-of-the-art, both on real DRAM chips and 2) two key security challenges of PiD: amplified DRAM read disturbance (e.g., 158x reduction in the minimum number of DRAM accesses required to induce the first bitflip) and high throughput memory timing channels (e.g., a communication throughput of 14.8Mb/s). We believe it is time to design, use, and program DRAM, and in general memory, not as an inactive storage substrate, but as a combined computation, storage, and security substrate, where computational capability, storage density, and security are all key goals.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 2 minor

Summary. The manuscript discusses the security benefits and challenges of Processing-in-DRAM (PiD), a memory-centric computing approach that exploits DRAM operational characteristics for in-memory computation. It reports new DRAM-based true random number generators (TRNGs) achieving up to 16.05 Gb/s throughput and physical unclonable functions (PUFs) with 5.75% lower evaluation latency than prior state-of-the-art, both demonstrated on real DRAM chips. It also identifies two key challenges: amplified read disturbance leading to a 158x reduction in the minimum accesses needed to induce the first bitflip, and high-throughput memory timing channels achieving 14.8 Mb/s. The work advocates designing DRAM as a combined computation, storage, and security substrate.

Significance. If the real-chip measurements hold, the paper provides a timely and concrete assessment of how shifting to memory-centric computing affects security, with specific quantitative examples of both new primitives and new attack surfaces. The grounding in hardware measurements on actual DRAM chips is a strength that could help guide secure PiD system design.

major comments (1)
  1. [Abstract] Abstract: The central quantitative claims (16.05 Gb/s TRNG throughput, 5.75% PUF latency reduction, 158x disturbance increase, 14.8 Mb/s channel) are presented as direct experimental observations with no reference to methods, number of chips/devices tested, controls, or statistical analysis. This information is load-bearing for the claims of new state-of-the-art primitives and specific quantified challenges.
minor comments (2)
  1. The manuscript would benefit from an explicit statement of which results are new versus drawn from prior work on DRAM-based security primitives.
  2. Figure and table captions should include enough detail to interpret the quantitative security metrics without referring back to the main text.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive comment and the recommendation of minor revision. We address the point on the abstract below.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The central quantitative claims (16.05 Gb/s TRNG throughput, 5.75% PUF latency reduction, 158x disturbance increase, 14.8 Mb/s channel) are presented as direct experimental observations with no reference to methods, number of chips/devices tested, controls, or statistical analysis. This information is load-bearing for the claims of new state-of-the-art primitives and specific quantified challenges.

    Authors: We agree that the abstract would benefit from explicit pointers to the experimental details. The methods, device counts, controls, and statistical analysis for all four quantitative results are already provided in the body of the manuscript (Sections 3 and 4). In the revised version we will add concise references in the abstract (e.g., “demonstrated on real DRAM chips; see Sections 3–4 for methods and analysis”) so that readers can immediately locate the supporting information without lengthening the abstract substantially. revision: yes

Circularity Check

0 steps flagged

No significant circularity identified

full rationale

The paper presents security benefits and challenges of Processing-in-DRAM as direct experimental observations from real DRAM chip measurements, including specific quantitative results for TRNG throughput (16.05 Gb/s), PUF latency improvements (5.75%), read disturbance amplification (158x), and timing channel throughput (14.8 Mb/s). No derivation chain, equations, fitted parameters, or self-referential steps are described; claims reduce to hardware measurements rather than any construction that equates outputs to inputs by definition or self-citation. The work is self-contained against external benchmarks as empirical reporting.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only review supplies no explicit free parameters, axioms, or invented entities; all quantitative claims rest on unstated experimental assumptions.

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discussion (0)

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