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5 Pith papers cite this work. Polarity classification is still indexing.

5 Pith papers citing it

years

2026 5

verdicts

UNVERDICTED 5

representative citing papers

SPEC CPU: The Next Generation

cs.PF · 2026-05-02 · unverdicted · novelty 7.0

SPEC CPU 2026 presents a new benchmark suite using open-source apps, expanded multithreading, and Rolling-Round-Robin Rate to address gaps in evaluating heterogeneous multiprogrammed CPU performance.

Scalable Packed Layouts for Vector-Length-Agnostic ML Code Generation

cs.PF · 2026-05-12 · unverdicted · novelty 6.0

Packed layouts and extensions to tiling/fusion/vectorization in MLIR/IREE enable VLA ML code generation for SVE, achieving up to 1.45x speedup over NEON and outperforming PyTorch frameworks while scaling with vector length.

Understanding Simulated Architecture via gem5 Call-Stack Profiling

cs.AR · 2026-05-02 · unverdicted · novelty 6.0

A specialized profiling tool using Linux perf_event samples gem5 call-stacks to expose simulated architecture behaviors such as TimingSimpleCPU inefficiencies and cache coherence deadlocks not visible in conventional stats.

Akita: A High Usability Simulation Framework for Computer Architecture

cs.DC · 2026-04-30 · unverdicted · novelty 5.0

Akita is a decoupled simulation engine that lets developers write simple single-threaded cycle-based code while automatically delivering event-driven performance, transparent parallel execution, and built-in tracing for monitoring and visualization.

citing papers explorer

Showing 5 of 5 citing papers.

  • SPEC CPU: The Next Generation cs.PF · 2026-05-02 · unverdicted · none · ref 29

    SPEC CPU 2026 presents a new benchmark suite using open-source apps, expanded multithreading, and Rolling-Round-Robin Rate to address gaps in evaluating heterogeneous multiprogrammed CPU performance.

  • Scalable Packed Layouts for Vector-Length-Agnostic ML Code Generation cs.PF · 2026-05-12 · unverdicted · none · ref 21

    Packed layouts and extensions to tiling/fusion/vectorization in MLIR/IREE enable VLA ML code generation for SVE, achieving up to 1.45x speedup over NEON and outperforming PyTorch frameworks while scaling with vector length.

  • Understanding Simulated Architecture via gem5 Call-Stack Profiling cs.AR · 2026-05-02 · unverdicted · none · ref 2

    A specialized profiling tool using Linux perf_event samples gem5 call-stacks to expose simulated architecture behaviors such as TimingSimpleCPU inefficiencies and cache coherence deadlocks not visible in conventional stats.

  • PG-MDP: Profile-Guided Memory Dependence Prediction for Area-Constrained Cores cs.PL · 2026-04-09 · unverdicted · none · ref 8

    Profile-guided opcode labeling removes consistently independent loads from the MDP working set, cutting queries 79%, false dependencies 77%, and raising small-core IPC 1.47% on SPEC2017 intspeed.

  • Akita: A High Usability Simulation Framework for Computer Architecture cs.DC · 2026-04-30 · unverdicted · none · ref 33

    Akita is a decoupled simulation engine that lets developers write simple single-threaded cycle-based code while automatically delivering event-driven performance, transparent parallel execution, and built-in tracing for monitoring and visualization.