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arxiv: 2604.15128 · v1 · submitted 2026-04-16 · 💻 cs.AR · cs.DC· cs.NI

Recognition: unknown

SCENIC: Stream Computation-Enhanced SmartNIC

Benjamin Ramhorst , Maximilian Jakob Heer , Luhao Liu , Heejae Kim , Jonas Dann , Jin-Soo Kim , Gustavo Alonso
Authors on Pith no claims yet

Pith reviewed 2026-05-10 09:43 UTC · model grok-4.3

classification 💻 cs.AR cs.DCcs.NI
keywords SmartNICstream computationRDMA offloadprogrammable datapathdatacenter networkingTCP/IP stackcollective communicationnetwork-to-GPU
0
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The pith

SCENIC turns the SmartNIC datapath into a first-class stream computation substrate to match commercial 200G performance while adding programmability.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Datacenter SmartNICs currently force a choice between commercial platforms that deliver high bandwidth and easy integration but limited customization, and research designs that often fall short on speed or compatibility. SCENIC closes this gap by treating the network datapath itself as a programmable stream computation substrate. It combines 200G offloaded TCP/IP and RDMA stacks with on-datapath Stream Compute Units for processing and embedded ARM cores for control, plus direct GPU and SSD access. The design stays fully compatible with existing Linux network and RDMA interfaces, so applications see no change yet can invoke custom offloads. A sympathetic reader would care because the result shows that meaningful programmability and control can be added without the latency or bandwidth penalties that usually accompany research prototypes.

Core claim

SCENIC implements a 200G network datapath over offloaded TCP/IP and RDMA stacks together with a fallback path for arbitrary traffic; on top of this logic it places Stream Compute Units for data processing and embedded ARM cores for flexible control-path manipulation, all while exposing native Linux network and RDMA verb interfaces so that the programmable elements remain transparent to unmodified applications.

What carries the argument

Stream Compute Units (SCUs) placed directly on the network datapath, paired with embedded ARM cores and shared hardware/software abstractions that allow tight co-design of infrastructure and applications.

Load-bearing premise

Adding Stream Compute Units and ARM cores to the high-speed datapath can deliver useful programmability and control without creating latency or bandwidth penalties that would keep the device from matching commercial SmartNIC performance.

What would settle it

A direct benchmark comparison in which SCENIC's measured latency or sustained bandwidth on standard RDMA or TCP workloads falls measurably below a commercial 200G SmartNIC, or in which the described use cases (offloaded collectives or network-to-GPU partitioning) cannot run at line rate.

Figures

Figures reproduced from arXiv: 2604.15128 by Benjamin Ramhorst, Gustavo Alonso, Heejae Kim, Jin-Soo Kim, Jonas Dann, Luhao Liu, Maximilian Jakob Heer.

Figure 1
Figure 1. Figure 1: Overview of SCENIC with two example offloads: hash-based network-to-GPU data partitioning (Section 9.2) and hybrid flow monitoring (Section 6.2). that, modern workloads require direct interaction with het￾erogeneous GPUs [81] and storage [15] at line rate. The challenge is doing so while also supporting in-network com￾pute. SCENIC demonstrates both: compliance with existing software (exposed as Linux netde… view at source ↗
Figure 2
Figure 2. Figure 2: Programmable congestion control in SCENIC. 5.2 Congestion control and network extensions Large-scale ML workloads expose the limitations of fixed congestion control algorithms [29, 50]. Programmable con￾gestion control (PCC), with scenario-adaptive algorithm se￾lection, addresses this challenge but requires direct modifica￾tion of the transport logic, which is restricted on commercial NICs. SCENIC’s open a… view at source ↗
Figure 3
Figure 3. Figure 3: DMA packet forwarding to the network driver. pipeline, classifying flows by source subnet to reflect pod￾level positions in Fat Tree topologies [5], while implementa￾tion dynamic policy decision making on the Arm cores. A hardware timer periodically interrupts the CPU, which reads traffic statistics via the AXI bus. A dynamically configurable SCU rate limiter then enforces the resulting policies. 7 Driver … view at source ↗
Figure 4
Figure 4. Figure 4: Performance evaluation of the fallback path. Left: ping latency. Right: iperf3 throughput. Hybrid refers to Mellanox-to-SCENIC communication. 7.2 ibv_device integration For data-intensive workloads, SCENIC includes a fully of￾floaded RoCEv2 stack and exposes itself as an ibv_device, ensuring compatibility with existing IB Verb applications (R2). This is realized through a two-component stack: (1) a kernel … view at source ↗
Figure 5
Figure 5. Figure 5: RDMA performance benchmark in a fully switched datacenter network. engines, resulting in slightly lower latencies. Despite this gap, SCENIC’s slow-path latency is well within the range re￾quired for management traffic: SSH sessions, monitoring, and control-plane communication remain fully responsive un￾der all tested conditions. A similar conclusion can be drawn for achievable throughput with iperf3 at a t… view at source ↗
Figure 6
Figure 6. Figure 6: Throughput of SCENIC to GPU with RDMA READs and RDMA WRITEs. 9 [PITH_FULL_IMAGE:figures/full_fig_p009_6.png] view at source ↗
Figure 8
Figure 8. Figure 8: Time series of bandwidth sharing scaling up to four parallel flows performing 128 KiB RDMA READs through separated SCUs. To demonstrate this design aspect, we configure SCENIC with four SCUs and run a throughput benchmark with 128 KiB RDMA READs. We incrementally scale the workload from one to four parallel flows, mapping each distinct flow to its own SCU [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Comparison of BROADCAST and GATHER collectives on SCENIC with OpenMPI on a commercial NIC. training [41, 55]; offloading them to the network can free up CPU cycles or reduce the GPU utilization [14]. Second, of￾floaded collectives create the possibility of collocating gradi￾ent compression as an in-network processing step to further overlap compute and communication [3]. For future work we plan to extend t… view at source ↗
Figure 10
Figure 10. Figure 10: Performance of hash partitioning on the CPU (B: Baseline, 1 and 16 threads) and offloaded with SCENIC. the multi-threaded software baseline compared to SCENIC￾offloaded hash partitioning. SCENIC offloading achieves la￾tency that scales linearly with data set size and, for larger transfer sizes, approaches the lower bound of just the RDMA communication. Throughput shows a fixed overhead at small data set s… view at source ↗
read the original abstract

Although modern, AI-centric datacenters heavily rely on SmartNICs, existing devices impose a hard trade-off. Commercial SmartNICs provide high bandwidth and easy software integration, but offer limited support for customization and data processing offload. In contrast, research SmartNICs often suffer from low bandwidth, limited functionality, and poor software compatibility -- to the point that many are not actual NICs in a technical sense. This gap can be closed by treating the NIC datapath as a first-class stream computation substrate with shared hardware/software abstractions for a tight co-design of infrastructure and applications. To demonstrate this, we introduce SCENIC, an open-source datacenter SmartNIC. SCENIC implements a 200G network datapath over offloaded TCP/IP and RDMA stacks, as well as a fallback path for processing arbitrary network traffic. On top of the network logic, SCENIC combines on-datapath Stream Compute Units (SCUs) for data processing and embedded ARM cores for flexible control path manipulation with direct access to GPUs and SSDs. SCENIC is fully integrated with the OS, exposing native Linux network and RDMA verb interfaces, making the programmable datapath transparent to existing applications while enabling control of, e.g., user-defined offloads and programmable congestion control. SCENIC's performance matches commercial platforms, and we show its versatility through several use cases such as offloaded collective communication and network-to-GPU hash-based data partitioning.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript introduces SCENIC, an open-source datacenter SmartNIC that implements a 200G network datapath over offloaded TCP/IP and RDMA stacks together with a fallback path for arbitrary traffic. It augments the datapath with on-datapath Stream Compute Units (SCUs) for data processing and embedded ARM cores for control, while providing direct GPU/SSD access and full integration with the Linux OS and RDMA verb interfaces. The central claims are that this design achieves performance parity with commercial platforms and enables versatile use cases such as offloaded collective communication and network-to-GPU hash-based data partitioning without sacrificing bandwidth or latency.

Significance. If the zero-overhead integration of SCUs and ARM cores is demonstrated, the work would meaningfully close the gap between high-bandwidth commercial SmartNICs and customizable research platforms by delivering a fully OS-compatible, programmable datapath. The open-source prototype, native Linux/RDMA compatibility, and multiple concrete use cases are positive attributes that could support broader adoption and further co-design research.

major comments (2)
  1. [Abstract] Abstract: The claim that 'SCENIC's performance matches commercial platforms' is load-bearing for the contribution yet is presented without any quantitative throughput, latency, or bandwidth measurements, error bars, baseline comparisons (e.g., to BlueField-class devices), or ablation data isolating the impact of the added SCUs and ARM cores versus pure bypass paths.
  2. [Use cases] Use-case demonstrations: The offloaded collective communication and hash-based GPU partitioning examples are described at a high level but lack performance numbers, comparisons against non-programmable baselines, or stress-test results on the programmable paths and fallback route under realistic 200G workloads, leaving the 'no-penalty' assumption unverified.
minor comments (1)
  1. [Abstract] Abstract: The acronym 'SCU' is introduced without a short definition or pointer to the stream-computation literature that motivates the hardware abstraction.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback and positive assessment of SCENIC's potential impact. We address each major comment below with point-by-point responses and indicate planned revisions.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The claim that 'SCENIC's performance matches commercial platforms' is load-bearing for the contribution yet is presented without any quantitative throughput, latency, or bandwidth measurements, error bars, baseline comparisons (e.g., to BlueField-class devices), or ablation data isolating the impact of the added SCUs and ARM cores versus pure bypass paths.

    Authors: We agree that the abstract would be strengthened by including a concise summary of the key quantitative results that appear in the evaluation section. The manuscript already contains throughput and latency measurements at 200 Gbps, direct comparisons to BlueField-class devices, error bars from repeated runs, and ablations isolating SCU/ARM overhead on the bypass path. We will revise the abstract to incorporate these supporting metrics and comparisons so the performance claim is substantiated at the abstract level as well. revision: yes

  2. Referee: [Use cases] Use-case demonstrations: The offloaded collective communication and hash-based GPU partitioning examples are described at a high level but lack performance numbers, comparisons against non-programmable baselines, or stress-test results on the programmable paths and fallback route under realistic 200G workloads, leaving the 'no-penalty' assumption unverified.

    Authors: The quantitative results for both use cases, including comparisons to non-programmable baselines and stress tests under full 200 Gbps load on programmable and fallback paths, are presented in the evaluation section. We acknowledge that the use-case descriptions themselves remain somewhat high-level and do not sufficiently cross-reference or restate these numbers. We will revise the use-case subsections to explicitly include the relevant performance figures, baseline comparisons, and workload results, thereby directly verifying the no-penalty claim in context. revision: yes

Circularity Check

0 steps flagged

No circularity detected in SCENIC implementation claims

full rationale

The paper presents an implemented hardware/software prototype for a 200G SmartNIC with on-datapath SCUs and ARM cores, offloaded TCP/IP/RDMA stacks, and OS integration. Central claims of matching commercial performance and versatility in use cases rest on the physical prototype, fallback paths, and demonstrated applications rather than any equations, fitted parameters, or derivations that reduce to their own inputs by construction. No self-definitional steps, uniqueness theorems, or ansatz smuggling via self-citation appear in the provided text; the design is described as a co-design substrate without load-bearing self-referential logic.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The design rests on standard domain assumptions about the feasibility of 200G networking hardware and RDMA offload; no free parameters, invented physical entities, or ad-hoc axioms are introduced in the abstract.

axioms (1)
  • domain assumption Existing hardware primitives for 200G networking and RDMA offload are sufficient to support the described performance and integration.
    The claims of matching commercial performance presuppose that the underlying silicon and protocol stacks behave as expected when augmented with SCUs and ARM cores.

pith-pipeline@v0.9.0 · 5580 in / 1438 out tokens · 36844 ms · 2026-05-10T09:43:46.936431+00:00 · methodology

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