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arxiv: 2604.18529 · v1 · submitted 2026-04-20 · 💻 cs.PF · cs.DC

Recognition: unknown

HybridGen: Efficient LLM Generative Inference via CPU-GPU Hybrid Computing

Dong Li, Guilherme Cox, Hyeran Jeon, Mao Lin, Xi Wang

Pith reviewed 2026-05-10 02:44 UTC · model grok-4.3

classification 💻 cs.PF cs.DC
keywords LLM inferenceKV cacheCPU-GPU hybridlong-context modelsattention computationtiered memoryCXLgenerative inference
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0 comments X

The pith

HybridGen lets CPUs and GPUs collaborate on attention for long-context LLMs with tiered memory, delivering 1.41x to 3.2x speedups over prior KV cache methods.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper proposes HybridGen as a way to handle the massive key-value caches that arise when large language models process thousands or millions of tokens. Existing methods either keep all attention work on the GPU or move it entirely to the CPU, which wastes hardware capacity and struggles with memory limits. HybridGen instead splits the attention calculations across CPU and GPU while using expanded memory tiers such as CXL for storage. It introduces attention logit parallelism, a feedback-driven scheduler, and semantic-aware KV cache mapping to coordinate the work. Experiments on three models with eleven sizes across three GPU platforms show faster inference with higher accuracy than six state-of-the-art alternatives.

Core claim

HybridGen is an efficient hybrid attention framework for long-context LLM inference that enables CPU-GPU collaborative attention on systems with expanded tiered memory. It addresses multi-dimensional attention dependencies, intensifying CPU-GPU load imbalance with longer sequences, and NUMA penalty of tiered memories through attention logit parallelism, a feedback-driven scheduler, and semantic-aware KV cache mapping. On three LLM models with eleven sizes tested on three GPU platforms with CXL-expanded memory, the framework outperforms six state-of-the-art KV cache management methods by 1.41x--3.2x on average while maintaining superior accuracy.

What carries the argument

Attention logit parallelism, a feedback-driven scheduler, and semantic-aware KV cache mapping, which together enable collaborative CPU-GPU attention computation and KV cache placement on tiered memory systems.

If this is right

  • Attention computation for very long sequences can be distributed rather than confined to a single processor type.
  • KV caches can be stored and partially processed across CPU, GPU, and CXL memory without relying on pruning or full offloading.
  • Dynamic scheduling based on runtime feedback can counteract load imbalance that grows with sequence length.
  • Semantic information about tokens can guide cache placement to reduce memory access penalties in tiered systems.
  • The same hardware can support longer contexts at higher throughput while preserving or improving generation quality.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The hybrid scheduling approach might extend to other memory-bound tasks that mix dense computation on accelerators with sparse access on general-purpose cores.
  • Semantic-aware placement could be combined with existing compression methods to push context lengths even further on the same hardware.
  • Hardware vendors might use these results to prioritize interconnect improvements that lower the NUMA costs the paper targets.
  • Similar feedback loops could help balance work in multi-device setups beyond the CPU-GPU-CXL configuration tested here.

Load-bearing premise

The three techniques of attention logit parallelism, feedback-driven scheduling, and semantic-aware KV cache mapping can jointly resolve multi-dimensional dependencies, CPU-GPU load imbalance, and NUMA penalties without unacceptable overhead or accuracy loss on varied models and hardware.

What would settle it

Running HybridGen on one of the tested GPU platforms with a sequence length beyond those evaluated and measuring either no speedup relative to GPU-only baselines or a drop in output accuracy would challenge the central performance and quality claims.

Figures

Figures reproduced from arXiv: 2604.18529 by Dong Li, Guilherme Cox, Hyeran Jeon, Mao Lin, Xi Wang.

Figure 1
Figure 1. Figure 1: KV cache memory consumption of OPT-13B across varying sequence lengths and batch sizes. The dashed line indicates the model’s weight size for comparison. To address the KV cache size exceeding GPU memory, prior studies proposed KV cache pruning [11, 19, 25] and offloading [16, 21, 33]. KV cache pruning retains only im￾portant tokens in GPU memory but risks accuracy loss from discarded context. Offloading p… view at source ↗
Figure 2
Figure 2. Figure 2: Estimated LLM inference time under various KV cache management: (1) Oracle case where GPU memory is large enough and attention can be done on GPU only, (2) Conventional KV cache offloading to CPU memory, where the KV caches are streamed to GPU from CPU memory everytime, (3) Advanced offloading where KV caches are prefetched to save migration overhead [33], (4) State-of-the￾art using selective attention whe… view at source ↗
Figure 3
Figure 3. Figure 3: LLM generative inference. • We evaluate HybridGen and six state-of-the-art KV cache management baselines with diverse LLMs in various sizes on three GPU platforms, with and without a CXL shared memory pool. HybridGen outperforms the compared so￾lutions by 1.41×–3.2× on average with superior accuracy. 2 Background 2.1 LLM Generative Inference LLM inference consists of two stages: prefill and generation (or … view at source ↗
Figure 4
Figure 4. Figure 4: Estimated data traffic during attention layer com￾putation per iteration under different strategies. 1K 2K 4K 8K 16K 32K 64K Sequence Length (Tokens) 0.0 0.5 1.0 1.5 Computation Load (FLOPs) 1e9 Attention on GPU HybridGen Attention on CPU GPU CPU [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Computation distribution on transformer block computation per iteration under different strategies. address space, and accessed by the host CPU or other accel￾erators (e.g., GPUs) via memory load/store instructions. Due to the extra PCIe and protocol latencies, CXL memories are known to be a few times slower than local memories. Thus, several studies introduced data mapping and prefetching algorithms betwe… view at source ↗
Figure 6
Figure 6. Figure 6: , AoG encounters higher data transfer latency while AoC suffers from at least 4× longer execution time than AoG due to CPU’s lower computational throughput. 3.4 CPU-GPU Hybrid Attention Computing The previous results show obvious limitations of both solu￾tions: AoG is constrained by memory capacity, while AoC is limited by compute capacity. This motivates CPU–GPU hybrid attention computing. In this design,… view at source ↗
Figure 7
Figure 7. Figure 7: Estimated latency of Grace-Hopper-like architec￾ture: Note that due to the limited GPU resource, AoG can not process longer sequences or larger batches (e.g., 3490 tokens with a batch size of 4), while the other two approaches can. </s> The quick brown fox jumps over the lazy dog Source (keys) </s> The quick brown fox jumps over the lazy dog Target (queries) opt-13b Attention L13 H9 0.0 0.2 0.4 0.6 0.8 1.0… view at source ↗
Figure 8
Figure 8. Figure 8: Heatmap of the attention scores from different layers in OPT-13B. 256 512 1024 2048 4096 8192 Sequence Length (Tokens) 0.0 0.5 1.0 1.5 Latency (s) Attention on GPU Attention on CPU HybridGen GPU compute CPU compute Data transfer [PITH_FULL_IMAGE:figures/full_fig_p004_8.png] view at source ↗
Figure 9
Figure 9. Figure 9 [PITH_FULL_IMAGE:figures/full_fig_p004_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Architecture of HybridGen. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Layer Index 0.2 0.4 0.6 0.8 1.0 Cosine Similarity OPT-6.7B (32 layers) Qwen2.5-7B (28 layers) Llama-3.1-8B (32 layers) [PITH_FULL_IMAGE:figures/full_fig_p005_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Cosine similarity between inputs of consecutive transformer layers (layer i vs. layer i+1) during decoding for OPT-6.7B, Qwen2.5-7B, and Llama-3.1-8B. (challenge 1) with Logits Calculator on CPU and Token Con￾catenator on GPU. Section 4.3 presents a novel Feedback Scheduler that dynamically balances CPU–GPU workloads as sequence length increases (challenge 2) to prevent CPU bottlenecks while preserving ac… view at source ↗
Figure 12
Figure 12. Figure 12: Workflow of HybridGen: ○1 While the GPU executes attention and the FFN for layer 𝑖, the CPU selects important tokens and computes attention logits for layer 𝑖 + 1 using the input of layer 𝑖, leveraging similarity across consecutive layers. ○2 -○3 The CPU transfers the computed logits and corresponding value vectors from tiered memory to the GPU. ○4 In parallel, the GPU computes logits for tokens cached in… view at source ↗
Figure 13
Figure 13. Figure 13: Attention logits computation under two token selection mechanism: Feedback scheduler chooses one of these at runtime to balance the performance. Algorithm 1 Feedback Scheduler Policy Require: GPU stage latency 𝑇gpu Require: CPU stage latency 𝑇cpu Require: Transfer latency 𝑇tx Require: Offline accuracy threshold 𝐾min Ensure: Token count 𝐾, selection strategy 1: Initialize 𝐾 ← 𝐾min 2: Initialize strategy ← … view at source ↗
Figure 15
Figure 15. Figure 15: End-to-end latency of different models. (Normalized to Baseline) CPU computes attention logits for offloaded tokens and gath￾ers corresponding value vectors, while the GPU computes logits for GPU-resident tokens, merges results in logical to￾ken order, applies softmax, and completes value aggregation and remaining transformer operations. Other components (e.g., model loading, batching, sampling, prefix ca… view at source ↗
Figure 17
Figure 17. Figure 17: Performance under different batch size. opt-1.3b opt-2.7b opt-6.7b opt-13b Avg. 0.8 0.9 1.0 1.1 Speedup Interleaving Mapping Semantic-aware Mapping [PITH_FULL_IMAGE:figures/full_fig_p010_17.png] view at source ↗
Figure 20
Figure 20. Figure 20: Accuracy under different KV cache pruning. 5.2.4 Impact of Semantic-Aware KV Cache Mapping [PITH_FULL_IMAGE:figures/full_fig_p010_20.png] view at source ↗
Figure 22
Figure 22. Figure 22: Accuracy under different feedback scheduler con￾figurations across varying datasets. CPU has room to process more tokens. However, as a longer context can be considered when a bigger 𝐾 is chosen, the adaptive 𝐾 selection shows superior accuracy than fixed 𝐾 configurations. When 𝐾 and selection timing are both chosen at runtime (Full Scheduler), the accuracy becomes significantly higher than the other meth… view at source ↗
read the original abstract

As modern LLMs support thousands to millions of tokens, KV caches grow to hundreds of gigabytes, stressing memory capacity and bandwidth. Existing solutions, such as KV cache pruning and offloading, alleviate these but underutilize hardware by relying solely on either GPU or CPU for attention computing, and considering yet limited CPU local memory for KV cache storage. We propose HybridGen, an efficient hybrid attention framework for long-context LLM inference. HybridGen enables CPU-GPU collaborative attention on systems with expanded tiered memory (e.g., CXL memory), addressing three key challenges: (1) multi-dimensional attention dependencies, (2) intensifying CPU-GPU load imbalance with longer sequences, and (3) NUMA penalty of tiered memories. HybridGen tackles these by introducing attention logit parallelism, a feedback-driven scheduler, and semantic-aware KV cache mapping. Experiments with three LLM models with eleven different sizes on three GPU platforms with a CXL-expanded memory show that HybridGen outperforms six state-of-the-art KV cache management methods by 1.41x--3.2x on average while maintaining superior accuracy.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper proposes HybridGen, a hybrid CPU-GPU attention framework for long-context LLM inference on tiered memory systems (e.g., CXL). It introduces attention logit parallelism, a feedback-driven scheduler, and semantic-aware KV cache mapping to address multi-dimensional attention dependencies, CPU-GPU load imbalance, and NUMA penalties. Experiments across three LLM models (eleven sizes) and three GPU platforms claim 1.41x–3.2x average speedups over six state-of-the-art KV cache management methods while preserving superior accuracy.

Significance. If the results hold under rigorous verification, the work offers a practical approach to scaling long-context inference by leveraging underutilized CPU resources and expanded memory tiers, potentially easing GPU memory capacity and bandwidth constraints in LLM serving.

major comments (2)
  1. Abstract: The central claims of 1.41x–3.2x speedups and accuracy preservation rest on experimental measurements, yet the abstract (and by extension the reported evaluation) provides no details on sequence lengths, error bars, exact baselines, or controls, undermining assessment of the performance claims.
  2. Evaluation section: No ablation studies, component-wise overhead breakdowns, or scaling curves for the feedback-driven scheduler and semantic-aware mapping as context length increases are presented; without these, it is impossible to confirm that the three techniques jointly resolve load imbalance and NUMA penalties without introducing offsetting latency or accuracy degradation.
minor comments (1)
  1. Abstract: The phrase 'superior accuracy' is used without defining the accuracy metric or the precise comparison points against the six baselines.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We are grateful to the referee for the thorough review and constructive suggestions. Below, we provide detailed responses to the major comments and outline the revisions we will make to address them.

read point-by-point responses

  1. Referee: [—] Abstract: The central claims of 1.41x–3.2x speedups and accuracy preservation rest on experimental measurements, yet the abstract (and by extension the reported evaluation) provides no details on sequence lengths, error bars, exact baselines, or controls, undermining assessment of the performance claims.

    Authors: We concur that the abstract would be strengthened by incorporating additional experimental details. Accordingly, we will revise the abstract to specify the sequence lengths used in our experiments (ranging from 4K to 512K tokens), list the exact six state-of-the-art baselines, and indicate that error bars represent standard deviations over multiple runs, with full controls and accuracy metrics provided in the Evaluation section. This will better contextualize the 1.41x–3.2x speedup claims. revision: yes

  2. Referee: [—] Evaluation section: No ablation studies, component-wise overhead breakdowns, or scaling curves for the feedback-driven scheduler and semantic-aware mapping as context length increases are presented; without these, it is impossible to confirm that the three techniques jointly resolve load imbalance and NUMA penalties without introducing offsetting latency or accuracy degradation.

    Authors: We acknowledge the value of ablation studies and component-wise analyses for validating the individual contributions of our proposed techniques. Although the manuscript presents comprehensive end-to-end results across diverse models and platforms, we agree that more granular breakdowns are beneficial. In the revised manuscript, we will add a dedicated subsection in the Evaluation section featuring: ablation studies isolating the effects of attention logit parallelism, the feedback-driven scheduler, and semantic-aware KV cache mapping; component-wise overhead breakdowns; and scaling curves demonstrating performance as context length increases. These will include measurements of load balance and NUMA-related penalties to confirm the techniques' effectiveness without introducing offsetting costs. revision: yes

Circularity Check

0 steps flagged

No circularity; empirical system evaluation with no self-referential derivations.

full rationale

The paper introduces HybridGen as a hybrid CPU-GPU attention framework using three techniques (attention logit parallelism, feedback-driven scheduler, semantic-aware KV cache mapping) to address multi-dimensional dependencies, load imbalance, and NUMA penalties on CXL-tiered systems. All central claims rest on direct empirical measurements across three LLM models (eleven sizes) and three GPU platforms, reporting 1.41x–3.2x average speedups versus six baselines while preserving accuracy. No mathematical derivation chain, equations, or first-principles predictions appear in the provided text that reduce to fitted parameters, self-definitions, or self-citations by construction. The evaluation is external and benchmark-driven, with no load-bearing steps that collapse to the inputs.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 3 invented entities

The paper introduces three new techniques as core contributions. No explicit free parameters are stated in the abstract. Relies on standard domain assumptions about attention computation and NUMA effects.

axioms (1)
  • domain assumption Standard assumptions about LLM attention computation and memory hierarchy in tiered systems hold without additional proof.
    Invoked implicitly when claiming the new techniques address the stated challenges.
invented entities (3)
  • attention logit parallelism no independent evidence
    purpose: Split attention computation across dimensions for hybrid CPU-GPU execution.
    New technique introduced to handle multi-dimensional dependencies.
  • feedback-driven scheduler no independent evidence
    purpose: Dynamically balance CPU-GPU load for longer sequences.
    New scheduler proposed to mitigate intensifying imbalance.
  • semantic-aware KV cache mapping no independent evidence
    purpose: Place cache entries to reduce NUMA penalties in tiered memory.
    New mapping strategy introduced for tiered memory systems.

pith-pipeline@v0.9.0 · 5500 in / 1434 out tokens · 48276 ms · 2026-05-10T02:44:19.990220+00:00 · methodology

discussion (0)

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