arxiv: 2604.26103 · v2 · submitted 2026-04-28 · 💻 cs.AR · cs.AI· cs.DC· cs.LG

Recognition: unknown

AMMA: A Multi-Chiplet Memory-Centric Architecture for Low-Latency 1M Context Attention Serving

Zhongkai Yu , Haotian Ye , Chenyang Zhou , Ohm Rishabh Venkatachalam , Zaifeng Pan , Zhengding Hu , Junsung Kim , Won Woo Ro

show 4 more authors

Po-An Tsai Shuyi Pei Yangwook Kang Yufei Ding

Authors on Pith no claims yet

Pith reviewed 2026-05-07 14:11 UTC · model grok-4.3

classification 💻 cs.AR cs.AIcs.DCcs.LG

keywords multi-chiplet architecturememory-centric designlong-context attentionLLM servingHBM-PNMdecode-phase optimizationhybrid parallelism

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The pith

A memory-centric multi-chiplet architecture replaces GPU dies with HBM-PNM cubes to cut attention latency for million-token contexts.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper claims that GPU-centered systems waste power and area on compute units idle during memory-bound decode attention, especially as contexts reach one million tokens. AMMA instead builds around HBM-PNM cubes that double available memory bandwidth and adds a logic-die microarchitecture plus two-level hybrid parallelism and reordered collective flow to convert that bandwidth into real gains. A sympathetic reader would see this as a direct attack on the primary latency bottleneck in long-context LLM serving. If correct, the design would let attention run at far lower latency and energy than current platforms without relying on compute-heavy GPUs.

Core claim

AMMA replaces GPU compute dies with HBM-PNM cubes to roughly double memory bandwidth for decode-phase attention. A logic-die microarchitecture exploits per-cube internal bandwidth under tight power and area limits, while a two-level hybrid parallelism scheme and reordered collective flow cut intra-chip communication costs. Design-space exploration over compute power and die-to-die link bandwidth guides hardware choices. The result is 15.5 times lower attention latency and 6.9 times lower energy use than a standard GPU baseline on long-context workloads.

What carries the argument

HBM-PNM cubes paired with a custom logic-die microarchitecture that routes decode attention directly to internal memory bandwidth, supported by two-level hybrid parallelism and reordered collective flow to minimize die-to-die traffic.

If this is right

Decode attention for 1M-token contexts becomes feasible at interactive latencies on memory-centric hardware.
Power and die area currently spent on idle compute units in GPUs can be reallocated to more memory bandwidth.
Hardware designers gain concrete guidance on per-cube compute power and intra-chip link bandwidth trade-offs.
Serving systems can shift from GPU-centric to memory-centric designs without losing attention performance.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The same memory-centric approach could apply to other memory-bound phases such as KV cache management or retrieval-augmented generation.
Future chiplet stacks might generalize the two-level parallelism pattern to additional AI primitives beyond attention.
If the bandwidth-to-performance translation holds, it suggests a broader shift away from compute-rich dies for inference workloads.

Load-bearing premise

The proposed logic-die microarchitecture, hybrid parallelism, and reordered flow can turn the extra per-cube bandwidth into proportional latency and energy reductions without large unmodeled overheads once built in silicon.

What would settle it

Fabricate a prototype of the AMMA chiplet stack, run 1M-token decode attention workloads on it, and compare measured latency and energy directly against an equivalent GPU baseline under identical conditions.

Figures

Figures reproduced from arXiv: 2604.26103 by Chenyang Zhou, Haotian Ye, Junsung Kim, Ohm Rishabh Venkatachalam, Po-An Tsai, Shuyi Pei, Won Woo Ro, Yangwook Kang, Yufei Ding, Zaifeng Pan, Zhengding Hu, Zhongkai Yu.

**Figure 1.** Figure 1: (a) Existing serving systems rely on GPUs for decode attention. AMMA replaces compute dies with HBM-PNM cubes view at source ↗

**Figure 2.** Figure 2: PIM/PNM architecture overview. (a) Compute and HBM BW utilization (b) Power breakdown (estimated) view at source ↗

**Figure 3.** Figure 3: Profiling of H100 (a) hardware utilization and (b) view at source ↗

**Figure 4.** Figure 4: A roofline analysis of Rubin and AMMA. 3.2 Power Breakdown of GPU To understand how GPUs spend their power budget, we profile an H100 running Qwen3-235B [61] attention at batch size 1, using NVML [39] for measurement and CACTI [35] for modeling. The result in view at source ↗

**Figure 6.** Figure 6: AMMA architecture hierarchy. (a) Package and cube level integration and (b) Core and SA level microarchitecture. view at source ↗

**Figure 7.** Figure 7: (a) Three conventional SA dataflows: WS, OS, IS. view at source ↗

**Figure 8.** Figure 8: Parallelism design for AMMA. (a) Naïve TP16 distributes every attention stage across all 16 cubes. (b) Our two-level view at source ↗

**Figure 9.** Figure 9: Reordered collective operation flow for proj O. (a) Default two-level hybrid flow. (b) Our reordered flow. view at source ↗

**Figure 10.** Figure 10: Decode latency speedup, normalized to H100. view at source ↗

**Figure 12.** Figure 12: Ablation study because RO yields a fixed latency reduction that is increasingly diluted by attention compute as sequences grow. Since most gains stem from reduced communication, view at source ↗

**Figure 13.** Figure 13: Per-layer decode latency breakdown on Qwen3 view at source ↗

**Figure 14.** Figure 14: Batch size exploration for Qwen3-235B at seq=64K. view at source ↗

read the original abstract

All current LLM serving systems place the GPU at the center, from production-level attention-FFN disaggregation to NVIDIA's Rubin GPU-LPU heterogeneous platform. Even academic PIM/PNM proposals still treat the GPU as the central hub for cross-device communication. Yet the GPU's compute-rich architecture is fundamentally mismatched with the memory-bound nature of decode-phase attention, inflating serving latency while wasting power and die area on idle compute units. The problem is compounded as reasoning and agentic workloads push context lengths toward one million tokens, making attention latency the primary user-facing bottleneck. To address these inefficiencies, we present AMMA, a multi-chiplet, memory-centric architecture for low-latency long-context attention. AMMA replaces GPU compute dies with HBM-PNM cubes, roughly doubling the available memory bandwidth to better serve memory-bound attention workloads. To translate this bandwidth into proportional performance gains, we introduce (i) a logic-die microarchitecture that fully exploits per-cube internal bandwidth for decode attention under a minimal power and area budget, (ii) a two-level hybrid parallelism scheme, and (iii) a reordered collective flow that reduces intra-chip die-to-die communication overhead. We further conduct a design-space exploration over per-cube compute power and intra-chip D2D link bandwidth, providing actionable guidance for hardware designers. Evaluations show that AMMA achieves 15.5X lower attention latency and 6.9X lower energy consumption compared with the NVIDIA H100.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

AMMA pushes a memory-centric HBM-PNM chiplet design for 1M-context decode attention with tailored logic dies and reordered collectives, but the 15.5X latency and 6.9X energy numbers rest on simulation assumptions that may undercount D2D and control overheads.

read the letter

The paper's main move is to stop treating the GPU as the central hub and instead center the system on HBM-PNM cubes that roughly double per-cube bandwidth for memory-bound attention. This directly targets the mismatch in current serving stacks where compute-rich dies sit idle during decode. The concrete contributions are the logic-die microarchitecture that tries to use internal bandwidth under tight power and area limits, the two-level hybrid parallelism scheme, and the reordered collective flow meant to cut intra-chip communication. They also run a design-space exploration on compute power and D2D link bandwidth, which gives hardware people some usable guidance on trade-offs. Those elements feel like genuine additions beyond prior PIM or GPU-disaggregated work. The headline results are 15.5X lower attention latency and 6.9X lower energy versus H100. If the underlying models are accurate, the gains would matter for long-context serving. The paper presents these as outcomes of the proposed components rather than fitted parameters, which is cleaner than some architecture papers. The soft spot is that the speedups assume the new microarchitecture and parallelism deliver near-ideal bandwidth use with only small unmodeled costs from die-to-die links, control logic, and scaling effects. The stress-test concern about realistic multi-chiplet overheads is reasonable here; without measured silicon data or more conservative modeling, the numbers stay projections. This is aimed at hardware architects and system designers working on next-generation accelerators, not at people who need immediate software changes. A reader already following PIM/PNM or memory-centric LLM hardware would get value from the details and the exploration. It deserves peer review because the problem statement is solid, the approach is distinct, and referees can pressure-test the simulation assumptions and suggest concrete validation steps.

Referee Report

1 major / 1 minor

Summary. The paper proposes AMMA, a multi-chiplet memory-centric architecture for low-latency 1M-context attention serving in LLMs. It replaces GPU compute dies with HBM-PNM cubes to roughly double per-cube memory bandwidth, introduces a logic-die microarchitecture optimized for decode attention under tight power/area budgets, a two-level hybrid parallelism scheme, and a reordered collective flow to minimize intra-chip D2D communication. A design-space exploration over per-cube compute power and D2D link bandwidth is performed, with evaluations claiming 15.5X lower attention latency and 6.9X lower energy consumption versus the NVIDIA H100.

Significance. If the performance claims hold after validation, the work would be significant for computer architecture and LLM systems research by directly targeting the memory-bound nature of long-context decode attention rather than relying on GPU-centric designs. The explicit design-space exploration over compute power and intra-chip D2D bandwidth provides actionable guidance for hardware designers and is a clear strength. The approach of using HBM-PNM cubes with custom logic dies offers a concrete alternative to current disaggregated serving systems.

major comments (1)

[Evaluation] Evaluation section: The headline claims of 15.5X latency reduction and 6.9X energy reduction versus H100 rest on the logic-die microarchitecture, two-level hybrid parallelism, and reordered collective flow converting doubled HBM bandwidth into proportional gains. However, the design-space exploration does not appear to include stress-testing against measured multi-chiplet D2D link latencies, control logic costs, or utilization losses at scale; without these, the proportional gains remain projections rather than demonstrated outcomes.

minor comments (1)

[Abstract] Abstract: The quantitative claims are presented without any reference to workloads, baseline configurations, or simulation methodology; adding a single sentence summarizing these would improve clarity for readers.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive feedback and for recognizing the significance of targeting memory-bound decode attention with a memory-centric multi-chiplet design. We address the single major comment below with clarifications on our evaluation methodology and modeling choices.

read point-by-point responses

Referee: [Evaluation] Evaluation section: The headline claims of 15.5X latency reduction and 6.9X energy reduction versus H100 rest on the logic-die microarchitecture, two-level hybrid parallelism, and reordered collective flow converting doubled HBM bandwidth into proportional gains. However, the design-space exploration does not appear to include stress-testing against measured multi-chiplet D2D link latencies, control logic costs, or utilization losses at scale; without these, the proportional gains remain projections rather than demonstrated outcomes.

Authors: We thank the referee for this observation. Our design-space exploration (Section 5) systematically varies intra-chip D2D link bandwidth over a wide range of values while holding other parameters fixed; this directly exercises the sensitivity of end-to-end latency and energy to communication performance, serving as a proxy for link-latency stress testing. The logic-die microarchitecture is deliberately minimal, with control logic area and power explicitly budgeted and subtracted from the per-cube envelope so that overheads are not ignored. Utilization is evaluated at full 1 M-token scale under the two-level hybrid parallelism and reordered collective schedule; the reported speedups already reflect the achieved utilization after all communication and synchronization costs. Because AMMA is a forward-looking proposal, we rely on validated cycle-accurate simulation rather than silicon measurements of future D2D links. We will add a short subsection in the revised manuscript that explicitly tabulates the control-logic overhead assumptions and includes an additional sensitivity sweep on utilization under pessimistic D2D latency assumptions. revision: partial

Circularity Check

0 steps flagged

No circularity: performance claims arise from design-space exploration of the proposed architecture, not from self-referential definitions or fitted inputs.

full rationale

The manuscript presents AMMA as a hardware architecture proposal whose latency and energy improvements versus H100 are obtained via design-space exploration over compute power and D2D bandwidth. No equations, fitted parameters, or self-citations appear as load-bearing steps that reduce the headline claims to their own inputs by construction. The central results are simulation outcomes of the described logic-die microarchitecture, hybrid parallelism, and reordered collectives; they are not tautological renamings or predictions forced by prior self-citations. External comparison to a commercial GPU further keeps the evaluation independent of the paper's own definitions.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only review yields no identifiable free parameters, axioms, or invented entities; the work rests on standard assumptions about HBM bandwidth scaling and D2D link costs that are not quantified here.

pith-pipeline@v0.9.0 · 5624 in / 1090 out tokens · 54009 ms · 2026-05-07T14:11:56.607029+00:00 · methodology

discussion (0)

Reference graph

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