Paper Citation Record · LEDGER

AutoChip: Automating HDL Generation Using LLM Feedback

As of 9 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 28 inbound Pith citation observations for arXiv:2311.04887.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2311.04887 v2

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 28 of 28 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-09T06:31:02.800959+00:00

measured 28 of 28 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-07T10:34:04.871248Z

measured 1 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-08-05T02:28:24.338817Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

17
arxiv_reference, observed 2026-08-05T02:28:24.338817Z

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 8e4f31c3-c924-4c78-b0cf-396b36af10f2 · inbound

QiMeng: Fully Automated Hardware and Software Design for Processor Chip cites this paper.

QiMeng: Fully Automated Hardware and Software Design for Processor Chip AutoChip: Automating HDL Generation Using LLM Feedback

Reference 122

Resolution: unresolved; no resolver link, observed 2026-08-07T10:34:04.871248Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3253158b-67d5-4e58-86b7-358c39133521 · inbound

Tools and Methodologies for System-Level Design cites this paper.

Tools and Methodologies for System-Level Design AutoChip: Automating HDL Generation Using LLM Feedback

Reference 93

Resolution: unresolved; no resolver link, observed 2026-08-06T17:54:18.040748Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2c03ee3c-32d0-430b-bc7f-c4a82d542620 · inbound

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation cites this paper.

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation AutoChip: Automating HDL Generation Using LLM Feedback

Reference 46

Resolution: unresolved; no resolver link, observed 2026-08-06T18:54:07.092977Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2ee24dd8-da72-4218-9edd-eb7b6fbc3eb1 · inbound

MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs cites this paper.

MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs AutoChip: Automating HDL Generation Using LLM Feedback

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-06T15:51:17.000553Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 5ff3cee7-c98d-4e92-8dbe-b2288c7b4a5b · inbound

EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code cites this paper.

EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code AutoChip: Automating HDL Generation Using LLM Feedback

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-06T22:33:17.305692Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ed0691f0-4c50-4e50-84f9-d6651403214d · inbound

FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design cites this paper.

FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design AutoChip: Automating HDL Generation Using LLM Feedback

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-06T14:49:56.535191Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 940ad1a5-aa06-439e-861b-192380c0f889 · inbound

Revolution or Hype? Seeking the Limits of Large Models in Hardware Design cites this paper.

Revolution or Hype? Seeking the Limits of Large Models in Hardware Design AutoChip: Automating HDL Generation Using LLM Feedback

Reference 31

Resolution: unresolved; no resolver link, observed 2026-08-05T05:50:29.879093Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 81053871-d0f4-485d-94aa-d42267425767 · inbound

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code cites this paper.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code AutoChip: Automating HDL Generation Using LLM Feedback

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:13.684192Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f3861127-de6f-4d8c-a7cd-e86656ce479e · inbound

MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design cites this paper.

MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design AutoChip: Automating HDL Generation Using LLM Feedback

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-04T16:31:32.445011Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation fb9aa621-83b8-42e8-a0c7-3d94c8847e6b · inbound

From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design cites this paper.

From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design AutoChip: Automating HDL Generation Using LLM Feedback

Reference 17

Resolution: verified exact; arxiv_id, observed 2026-05-10T06:06:18.442613Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 34e88bd3-f00c-4f8b-9ea9-1797e3ec6454 · inbound

VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation cites this paper.

VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation AutoChip: Automating HDL Generation Using LLM Feedback

Reference 13

Resolution: verified exact; arxiv_id, observed 2026-05-11T12:11:06.944979Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation c1a72df5-5805-447d-b44f-9cd15216ed3d · inbound

ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration cites this paper.

ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration AutoChip: Automating HDL Generation Using LLM Feedback

Reference 7

Resolution: verified exact; arxiv_id, observed 2026-05-11T13:36:08.338841Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation fd0a3cf2-15d8-4a5b-b2b2-7c05f22acebb · inbound

AnalogMaster: Large Language Model-based Automated Analog IC Design Framework from Image to Layout cites this paper.

AnalogMaster: Large Language Model-based Automated Analog IC Design Framework from Image to Layout AutoChip: Automating HDL Generation Using LLM Feedback

Reference 15

Resolution: metadata mismatch; arxiv_id, observed 2026-05-11T13:51:05.010781Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation c3d9d45e-ef5d-48e0-b56e-8734ace5d7ac · inbound

LEGO: An LLM Skill-Based Front-End Design Generation Platform cites this paper.

LEGO: An LLM Skill-Based Front-End Design Generation Platform AutoChip: Automating HDL Generation Using LLM Feedback

Reference 26

Resolution: verified exact; arxiv_id, observed 2026-05-11T20:41:10.254229Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 15294d9b-5e76-4ab0-a689-e58456b7d040 · inbound

LEGO: An LLM Skill-Based Front-End Design Generation Platform cites this paper.

LEGO: An LLM Skill-Based Front-End Design Generation Platform AutoChip: Automating HDL Generation Using LLM Feedback

Reference 26

Resolution: verified exact; arxiv_id, observed 2026-05-21T09:19:56.711478Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 90244040-d234-497e-9eed-58b8597a7ad1 · inbound

ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards cites this paper.

ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards AutoChip: Automating HDL Generation Using LLM Feedback

Reference 12

Resolution: verified exact; arxiv_id, observed 2026-07-02T20:27:22.719132Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation f4cbd62f-d096-4c6b-8d8f-96330f1bea6e · inbound

RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models cites this paper.

RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models AutoChip: Automating HDL Generation Using LLM Feedback

Reference 34

Resolution: verified exact; arxiv_id, observed 2026-07-03T00:47:30.481041Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 7921a70c-0e9f-4009-a1d9-74c472a98254 · inbound

Surveying GenAI-based Automation in Printed Circuit Board Design and Test cites this paper.

Surveying GenAI-based Automation in Printed Circuit Board Design and Test AutoChip: Automating HDL Generation Using LLM Feedback

Reference 101

Resolution: verified exact; arxiv_id, observed 2026-06-27T08:20:45.256957Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 8c8dd6be-c77c-4379-81db-87050c9f1060 · inbound

Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement cites this paper.

Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement AutoChip: Automating HDL Generation Using LLM Feedback

Reference 42

Resolution: verified exact; arxiv_id, observed 2026-07-03T21:28:59.396141Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation f2d28ebf-2a42-48dc-aad0-285427d3f170 · inbound

Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement cites this paper.

Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement AutoChip: Automating HDL Generation Using LLM Feedback

Reference 42

Resolution: unresolved; no resolver link, observed 2026-07-15T10:45:43.149976Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e234141f-21e9-4b19-b837-2ff72a84c307 · inbound

PCB-QA: Evaluating LLMs over the First Printed Circuit Board Design Question-Answer Dataset cites this paper.

PCB-QA: Evaluating LLMs over the First Printed Circuit Board Design Question-Answer Dataset AutoChip: Automating HDL Generation Using LLM Feedback

Reference 41

Resolution: verified exact; arxiv_id, observed 2026-06-27T08:20:44.881766Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 6d02e71b-bd8f-48d3-9fa6-7275399dabfd · inbound

VeriPilot: An LLM-Powered Verilog Debugging Framework cites this paper.

VeriPilot: An LLM-Powered Verilog Debugging Framework AutoChip: Automating HDL Generation Using LLM Feedback

Reference 12

Resolution: verified exact; arxiv_id, observed 2026-07-04T12:39:49.552944Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 00caa813-2096-4a8c-ad40-c391a690b52e · inbound

Agentic Hardware Design as Repository-Level Code Evolution cites this paper.

Agentic Hardware Design as Repository-Level Code Evolution AutoChip: Automating HDL Generation Using LLM Feedback

Reference 14

Resolution: verified exact; arxiv_id, observed 2026-07-01T18:45:58.327141Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 6b826155-be80-4812-9c80-7a3d9594b5c2 · inbound

SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence cites this paper.

SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence AutoChip: Automating HDL Generation Using LLM Feedback

Reference 1

Resolution: verified exact; arxiv_id, observed 2026-07-03T17:38:43.480766Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 2764c245-bd25-4bf7-940d-669c596679ec · inbound

ArchEval: Measuring AI Agents as Computer Architects cites this paper.

ArchEval: Measuring AI Agents as Computer Architects AutoChip: Automating HDL Generation Using LLM Feedback

Reference 45

Resolution: unresolved; no resolver link, observed 2026-07-12T01:16:50.927415Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2fc94877-60df-443b-98a2-571a69580b3c · inbound

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation cites this paper.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation AutoChip: Automating HDL Generation Using LLM Feedback

Reference 21

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:18.056245Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 4f08f9b3-2d9d-48c5-9208-7a17edf9b90f · inbound

DRC-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models cites this paper.

DRC-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models AutoChip: Automating HDL Generation Using LLM Feedback

Reference 21

Resolution: unresolved; no resolver link, observed 2026-08-01T06:38:42.551394Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 48c82e9d-e158-4cd3-99db-c1da535d5301 · inbound

VClare: Resolving Imperfect Specifications in LLM-Based Verilog Generation cites this paper.

VClare: Resolving Imperfect Specifications in LLM-Based Verilog Generation AutoChip: Automating HDL Generation Using LLM Feedback

Reference 17

Resolution: unresolved; no resolver link, observed 2026-07-30T23:35:19.832385Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.