A Reference-less Slope Detection Technique in 65nm for Robust Sensing of 1T1R Arrays

Anirudh Iyengar; Jae-Won Jang; Rekha Govindaraj; Seyedhamidreza Motaman; Swaroop Ghosh; Zakir Khondker

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arxiv 2306.03972 v1 pith:L44VVADO submitted 2023-06-06 cs.ET cs.AR

A Reference-less Slope Detection Technique in 65nm for Robust Sensing of 1T1R Arrays

Seyedhamidreza Motaman , Swaroop Ghosh , Jae-Won Jang , Anirudh Iyengar , Rekha Govindaraj , Zakir Khondker This is my paper

classification cs.ET cs.AR

keywords sensingslopearraydetectionk-5kprocessreference-lessstate

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Spin-Torque-Transfer RAM (STTRAM) is a promising technology however process variation poses serious challenge to sensing. To eliminate bit-to-bit process variation we propose a reference-less, destructive slope detection technique which exploits the MTJ switching from high to low state to detect memory state. A proof-of-concept fabricated test-chip using 96kb mimicked STTRAM bits in 65nm technology shows that slope sensing reduces failure rate by 120X in 2.5K-5K array@TMR=100% and 162X in 2.5K-5K@TMR=80% array compared to conventional voltage sensing.

A Reference-less Slope Detection Technique in 65nm for Robust Sensing of 1T1R Arrays

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