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arxiv: 2605.01352 · v1 · submitted 2026-05-02 · 💻 cs.OS · cs.AI· cs.DC

Recognition: unknown

VUDA: Breaking CUDA-Vulkan Isolation for Spatial Sharing of Compute and Graphics on the Same GPU

Bin Xu , Pengfei Hu , Wenxin Zheng , Jinyu Gu , Haibo Chen
Authors on Pith no claims yet

Pith reviewed 2026-05-10 15:58 UTC · model grok-4.3

classification 💻 cs.OS cs.AIcs.DC
keywords CUDAVulkanGPU spatial sharingexecution isolationchannel redirectionpage table graftingembodied AI simulation
0
0 comments X

The pith

VUDA breaks CUDA-Vulkan isolation by redirecting channels and grafting page tables to enable spatial sharing of compute and graphics on one GPU.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that CUDA and Vulkan workloads can execute concurrently on the same GPU instead of alternating in exclusive time slices. Although the two APIs present different abstractions to programmers, their paths meet at a shared channel primitive in the driver, and their virtual address spaces do not overlap. VUDA therefore redirects CUDA streams into Vulkan's scheduling domain and merges the page tables without any address remapping or data copying on the critical path. A thin annotation API lets developers mark co-schedulable streams. In embodied-AI workloads that interleave physics simulation and photorealistic rendering, the approach raises throughput by as much as 85 percent while improving GPU utilization and lowering end-to-end latency.

Core claim

Although CUDA and Vulkan expose different programming abstractions, their execution paths converge to a common channel primitive at the driver and hardware level, and their virtual-address spaces are inherently disjoint. VUDA exploits these facts through channel redirection into Vulkan's scheduling domain and page-table grafting to unify address spaces, thereby allowing spatial parallelism between compute and graphics workloads while eliminating all data copying on the critical path.

What carries the argument

Channel redirection and page-table grafting that unify CUDA and Vulkan execution paths at the driver level.

If this is right

  • Developers can annotate co-schedulable CUDA streams to run concurrently with Vulkan graphics without changing existing kernels.
  • Compute and graphics workloads no longer occupy mutually exclusive time slices, raising overall GPU utilization.
  • End-to-end latency drops for pipelines that alternate simulation and rendering phases.
  • Throughput rises up to 85 percent relative to temporal-sharing baselines on representative embodied-AI tasks.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same redirection-plus-grafting pattern could be applied to other pairs of compute and graphics APIs that share comparable low-level driver primitives.
  • Unified scheduling across APIs might simplify future hardware designs that currently maintain separate scheduling domains.
  • Mixed workloads on mobile or embedded GPUs could see similar utilization gains if the address-space disjointness property holds across those platforms.

Load-bearing premise

CUDA and Vulkan execution paths converge to a common channel primitive at the driver and hardware level with inherently disjoint virtual-address spaces.

What would settle it

Page-table merging that produces address conflicts or channel redirection that still forces exclusive time slices in hardware would show the spatial-sharing mechanism does not work safely without remapping.

Figures

Figures reproduced from arXiv: 2605.01352 by Bin Xu, Haibo Chen, Jinyu Gu, Pengfei Hu, Wenxin Zheng.

Figure 1
Figure 1. Figure 1: SM utilization trace for a ManiSkill data￾generation workload. The simulation phase (green, action sampling+simulation) and the rendering phase (red, render) alternate sequentially, with SM utilization below 10% during simulation and peaking near 70% during rendering. • We identify parallelism opportunities in two foundational embodied-AI scenarios—simulation data generation and RL training—and show that b… view at source ↗
Figure 3
Figure 3. Figure 3: Code modifications for data generation and RL training. Changed lines are marked with + and -. 3 VUDA Programming Interface This section describes how application developers use VUDA. We first elaborate on the parallelism opportunities existing in embodied-AI simulation workloads (Insight 1), then present the VUDA API and show how it is integrated into each rep￾resentative scenario. 3.1 Parallelism Pattern… view at source ↗
Figure 4
Figure 4. Figure 4: Channel redirection. In the default configura￾tion (left), CUDA streams and Vulkan queues are backed by channels in separate TSGs, preventing spatial co-execution. VUDA unplugs a CUDA stream from its native channel and plugs it into a forwarding channel in the Vulkan context (right), so both submission paths share the same TSG. that redirected kernels can resolve CUDA virtual addresses without any data cop… view at source ↗
Figure 5
Figure 5. Figure 5: Page-table grafting. VUDA recursively merges PDEs from CUDA’s page directory into Vulkan’s. Shared sub￾tree pointers (dashed arrows) ensure that PTE-level changes are visible to both contexts without additional propagation. L4 PTEs are omitted. a CUDA kernel dispatched on a Vulkan channel will fault or produce incorrect results. To close this gap, VUDA implements a one-time bootstrap￾ping step per channel:… view at source ↗
Figure 6
Figure 6. Figure 6: Cost of sharing GPU memory between CUDA and Vulkan: page-table grafting vs. the standard export/import path, measured over an increasing number of 2 MB buffers (log–log scale). RM driver modifications. Beyond the UVM module, we make two targeted modifications to the resource manager driver. First, we add a new RM control command that al￾lows user-space to query the virtual address space handle associated w… view at source ↗
Figure 7
Figure 7. Figure 7: Data-generation throughput (k steps/s) across five ManiSkill environments at 640×480 resolution. VUDA enables inter-step pipelining of simulation and rendering, with gains increasing as the batch size grows and the two phases become more balanced. Act+Sim(K-1) Act+Sim(K) Act+Sim(K+1) ⋯ ⋯ Render(K-1) Render(K) Render(K+1) [PITH_FULL_IMAGE:figures/full_fig_p010_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: SM utilization trace with VUDA enabled (same workload as [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗
Figure 10
Figure 10. Figure 10: VLA-based RL rollout throughput speedup on RTX 6000 Pro with VUDA enabled across parallel￾environment counts [PITH_FULL_IMAGE:figures/full_fig_p011_10.png] view at source ↗
read the original abstract

GPU-based simulation environments for embodied AI interleave physics simulation (CUDA) and photorealistic rendering (Vulkan) on a single device. We observe that two foundational scenarios -- simulation data generation and RL training -- can be naturally adapted to execute their simulation and rendering phases concurrently, presenting a significant opportunity to improve GPU utilization through spatial multiplexing. However, a fundamental obstacle we term execution isolation prevents this: CUDA and Vulkan create separate GPU contexts whose channels are bound to different scheduling groups, confining compute and graphics to mutually exclusive time slices. Existing spatial-sharing techniques are limited to the CUDA ecosystem, while temporal-sharing approaches underutilize available resources. This paper presents VUDA, a system that breaks execution isolation to enable spatial parallelism between CUDA compute and Vulkan graphics workloads. VUDA is built on two key observations: although CUDA and Vulkan expose different programming abstractions, their execution paths converge to a common channel primitive at the driver and hardware level; meanwhile, their virtual-address spaces are inherently disjoint, making safe page-table merging feasible without remapping. VUDA exposes a thin API for developers to annotate co-schedulable CUDA streams, and realizes spatial sharing through channel redirection into Vulkan's scheduling domain and page-table grafting to unify address spaces, eliminating all data copying on the critical path. Experiments on representative embodied-AI workloads show that VUDA delivers up to 85% higher throughput than temporal-sharing baselines, while improving GPU utilization and reducing end-to-end latency.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript proposes VUDA, a system that breaks CUDA-Vulkan execution isolation to enable spatial sharing of compute (CUDA) and graphics (Vulkan) workloads on a single GPU. It relies on two observations: execution paths converge to a common channel primitive at the driver/hardware level, and virtual-address spaces are inherently disjoint, allowing safe page-table grafting without remapping or data copies. VUDA exposes a thin annotation API for co-schedulable CUDA streams and redirects channels into Vulkan's domain. Experiments on embodied-AI workloads (simulation data generation and RL training) report up to 85% higher throughput than temporal-sharing baselines, along with improved GPU utilization and reduced end-to-end latency.

Significance. If the mechanism is correct and the performance results hold under scrutiny, VUDA would offer a practical way to improve GPU utilization in mixed compute-graphics pipelines common to embodied AI, robotics simulation, and RL training. The work identifies a concrete opportunity to leverage low-level driver convergence rather than remaining confined to single-API spatial sharing or inefficient temporal multiplexing.

major comments (2)
  1. [Abstract and §3] Abstract and §3 (mechanism description): The central claim that CUDA and Vulkan virtual-address spaces are 'inherently disjoint' and converge to a 'common channel primitive' is stated as an observation but receives no verification step, address-space audit, collision-handling logic, or fallback for driver/GPU/version-specific overlaps. This assumption is load-bearing for the correctness of page-table grafting; without it, the redirection could produce invalid mappings or silently fall back to serialization.
  2. [§5] §5 (evaluation): The headline result of 'up to 85% higher throughput' is presented without workload descriptions, hardware details, baseline implementations, number of runs, error bars, or ablation data isolating the contribution of spatial sharing. This absence makes the performance claim impossible to assess or reproduce from the manuscript.
minor comments (1)
  1. The term 'execution isolation' is introduced in the abstract without a concise definition or pointer to the relevant driver-level scheduling groups, which would aid readers outside the immediate GPU-systems community.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive and detailed feedback. We address each major comment below, indicating the revisions planned for the next version of the manuscript.

read point-by-point responses

  1. Referee: [Abstract and §3] Abstract and §3 (mechanism description): The central claim that CUDA and Vulkan virtual-address spaces are 'inherently disjoint' and converge to a 'common channel primitive' is stated as an observation but receives no verification step, address-space audit, collision-handling logic, or fallback for driver/GPU/version-specific overlaps. This assumption is load-bearing for the correctness of page-table grafting; without it, the redirection could produce invalid mappings or silently fall back to serialization.

    Authors: We appreciate the referee highlighting the need for explicit verification of this load-bearing assumption. The claims are grounded in our examination of driver source code, hardware specifications, and empirical testing across multiple driver versions, which showed convergence to shared channel primitives and disjoint virtual address spaces. To strengthen the manuscript, we will revise §3 to add a dedicated verification subsection. This will describe the address-space audit methodology, document any identified collision risks, and detail the implemented fallback to serialization when overlaps are detected. We believe this addition will address the correctness concerns without altering the core mechanism. revision: yes

  2. Referee: [§5] §5 (evaluation): The headline result of 'up to 85% higher throughput' is presented without workload descriptions, hardware details, baseline implementations, number of runs, error bars, or ablation data isolating the contribution of spatial sharing. This absence makes the performance claim impossible to assess or reproduce from the manuscript.

    Authors: We agree that the current presentation of results in §5 lacks sufficient detail for full assessment and reproducibility. In the revised manuscript we will expand the evaluation section to include complete workload descriptions for the embodied-AI simulation and RL tasks, exact hardware specifications (GPU models, driver versions), references or descriptions of the temporal-sharing baselines, the number of runs performed, error bars or confidence intervals, and ablation experiments that isolate the contributions of channel redirection and page-table grafting. These changes will make the 85% throughput improvement claim verifiable and reproducible. revision: yes

Circularity Check

0 steps flagged

No circularity: system design and empirical results stand independently of self-referential definitions or fitted inputs.

full rationale

The paper is a systems implementation work with no equations, no fitted parameters renamed as predictions, and no derivation chain that reduces to its own inputs. Key premises (convergence to a common channel primitive and inherently disjoint VA spaces) are presented as observations enabling the design, with throughput and utilization claims resting on described mechanisms plus experimental outcomes. No self-citation load-bearing steps, uniqueness theorems, or ansatzes appear in the provided text. The contribution is self-contained as an engineering artifact evaluated against baselines.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The central claim rests on two hardware/driver assumptions stated as observations; no free parameters or new entities are introduced.

axioms (2)
  • domain assumption CUDA and Vulkan execution paths converge to a common channel primitive at the driver and hardware level
    Explicitly listed as one of the two key observations enabling the design.
  • domain assumption CUDA and Vulkan virtual-address spaces are inherently disjoint
    Stated as the second key observation that makes page-table grafting safe without remapping.

pith-pipeline@v0.9.0 · 5578 in / 1210 out tokens · 43810 ms · 2026-05-10T15:58:22.584019+00:00 · methodology

discussion (0)

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