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arxiv: 2606.28565 · v1 · pith:CVBUA33Lnew · submitted 2026-06-26 · 💻 cs.PF · cs.AI· cs.AR

KernelSight-LM: A Kernel-Level LLM Inference Simulator

Xiteng Yao , Taeho Kim , Hengzhi Pei , Xinle Liu , Kyle Ulrich , Leonard Lausen , Ashish Khetan , Xiang Song
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George Karypis Martin Herbordt
This is my paper

Pith reviewed 2026-06-30 00:44 UTC · model grok-4.3

classification 💻 cs.PF cs.AIcs.AR
keywords LLM inference simulationkernel latency predictionGPU performance modelingroofline analysisdiscrete-event schedulingserving systemshardware co-designcontinuous batching
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The pith

KernelSight-LM predicts per-kernel LLM inference latency on unseen GPU generations to 12.1% error with no target measurements.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces a simulator that decomposes LLM serving steps into roofline kernel execution, communication, and host overhead components scheduled by a discrete-event system that also handles prefix caching and continuous batching. It offers a cross-generation prediction mode that relies solely on hardware specifications and microbenchmarks from earlier GPUs rather than any measurements on the target device. A sympathetic reader would care because current practice requires slow, deployment-specific on-device benchmarking that does not generalize across hardware generations or serving configurations. The work shows this decomposition yields end-to-end median errors of 15.4% for TTFT, 12.8% for TPOT, and 3.0% for throughput across six model families in the cross-generation tier.

Core claim

KernelSight-LM decomposes each serving step into a roofline kernel model with a learned efficiency term, a communication model, and a host-overhead model, composed through a discrete-event scheduler that captures prefix caching and continuous batching. The cross-generation tier uses only hardware specifications and kernel microbenchmarks from previously profiled GPUs to predict per-kernel latency on an unseen GPU generation to 12.1% error, a 1.8x improvement over the roofline baseline of 22.0%. The target-measured tier adds one model-agnostic kernel-microbenchmark sweep on the target GPU to reach 3.8% per-kernel error.

What carries the argument

Roofline kernel model with a learned efficiency term fitted from microbenchmarks, composed with communication and host-overhead models via a discrete-event scheduler.

If this is right

  • End-to-end median errors reach 15.4% TTFT, 12.8% TPOT, and 3.0% throughput in cross-generation mode across six model families.
  • Target-measured mode sharpens per-kernel error to 3.8% with a single model-agnostic microbenchmark sweep.
  • Kernel-level bottleneck breakdowns directly support hardware and software co-design decisions.
  • Both tiers require far less target-GPU data collection than prior profiling systems they extend.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same decomposition could be tested on non-GPU accelerators if the roofline-plus-efficiency structure holds.
  • Capacity planning tools could ingest the kernel breakdowns to estimate cluster sizing before hardware purchase.
  • Serving policy designers could iterate on batching and caching rules using simulated traces instead of repeated deployments.

Load-bearing premise

The efficiency term learned from microbenchmarks on previously profiled GPUs generalizes to new GPU generations and diverse serving workloads without target-specific measurements or retraining.

What would settle it

Running the cross-generation tier on a new GPU generation and observing per-kernel prediction error that exceeds 12.1% or fails to beat the 22.0% roofline baseline by a substantial margin would falsify the central claim.

Figures

Figures reproduced from arXiv: 2606.28565 by Ashish Khetan, George Karypis, Hengzhi Pei, Kyle Ulrich, Leonard Lausen, Martin Herbordt, Taeho Kim, Xiang Song, Xinle Liu, Xiteng Yao.

Figure 1
Figure 1. Figure 1: A GPU is an array of streaming multiprocessors [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Wave quantization. A kernel’s 𝐵 thread blocks are scheduled onto the 𝑁SM SMs in waves; when 𝐵 is not a multiple of 𝑁SM the final wave is partial and leaves SMs idle (here 9 blocks on 4 SMs span 3 waves, leaving 3 of 4 SMs idle in the last), inflating execution time by 𝑢 = ⌈𝐵/𝑁SM⌉ 𝑁SM/𝐵 ≥ 1 in the compute roofline (Eq. (2)) [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: An example of a roofline plot of A100 GPU. [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: An overview of KernelSight-LM’s architecture. The left-hand input boxes are the data the user provides (hardware [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Our per-kernel latency prediction workflow. [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: The bounded analytical head adapted from [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: NVLink and PCIe differ in absolute bandwidth, but [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Kernel-time composition over an example single request’s progress (Qwen3-8B, GB200). During prefill, GEMM [PITH_FULL_IMAGE:figures/full_fig_p008_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: GB200 real-vs-sim accuracy across select serving runs (models [PITH_FULL_IMAGE:figures/full_fig_p010_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: The cross-generation test. Per-kernel 𝜂 = measured/roofline versus each family’s dominant shape parameter, across six GPUs. The five analysis devices are gray; GB200 (blue) is the held-out target. Where GB200’s curve lies within the analysis envelope (GEMM), 𝜂 interpolates; where it lies apart (attention, KV-cache, RoPE), 𝜂 is device-specific and cannot be recovered from the other devices. Dashed: GB200’s… view at source ↗
Figure 11
Figure 11. Figure 11: When 𝜂 extrapolates. Each family placed by 𝜂 magnitude (geomean over devices; 1 = roofline exact) and cross-device spread (max/min; 1 = portable). The safe region (blue) holds families where the roofline is accurate and 𝜂 ports; the danger region (orange) holds those where 𝜂 both carries the prediction and varies across devices [PITH_FULL_IMAGE:figures/full_fig_p016_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Prediction error vs. offered load (One run of Qwen3, TP1, GB200). [PITH_FULL_IMAGE:figures/full_fig_p017_12.png] view at source ↗
read the original abstract

As large language models (LLMs) move into production serving, practitioners must rapidly evaluate inference performance across diverse hardware, models, and serving parameters to meet cost and latency targets. However, the end-to-end behavior of LLMs couples serving-layer policies with low-level GPU kernel execution and rapidly evolving architectures, forcing slow, deployment-specific benchmarking that is hard to generalize. We present KernelSight-LM, a fine-grained inference simulator that models token-level execution and produces kernel-level latency breakdowns. It decomposes each serving step into a roofline kernel model with a learned efficiency term, a communication model, and a host-overhead model, composed through a discrete-event scheduler that also captures mechanisms like prefix caching and continuous batching. KernelSight-LM offers two prediction tiers that trade target-GPU data for accuracy. The cross-generation tier uses no target-GPU measurements, only hardware specifications and kernel microbenchmarks from previously profiled GPUs, and predicts per-kernel latency on an unseen GPU generation to 12.1% error, a 1.8x improvement over the roofline baseline (22.0%). A second target-measured tier adds one model-agnostic kernel-microbenchmark sweep on the target GPU, sharpening per-kernel error to 3.8%, a 7.3x improvement over a comparable baseline (27.7%). Both tiers require far less target-GPU data than the prior systems they extend. In our simulator, these predictions yield end-to-end median (p50) errors across six model families of 15.4%, 12.8%, and 3.0% (TTFT, TPOT, throughput) in the cross-generation tier and 14.3%, 6.2%, and 2.7% in the target-measured tier, matching dedicated profiling tools while collecting far less on-device data. Beyond prediction, its kernel-level bottleneck breakdowns support hardware/software co-design and capacity planning.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 2 minor

Summary. The manuscript presents KernelSight-LM, a simulator for LLM inference performance that models token-level execution by decomposing each serving step into a roofline-based kernel model augmented with a learned efficiency term, a communication model, and a host-overhead model. These are composed using a discrete-event scheduler that incorporates serving mechanisms such as prefix caching and continuous batching. The system provides two prediction tiers: a cross-generation tier that uses only hardware specifications and prior GPU microbenchmarks to predict per-kernel latencies on unseen GPU generations with 12.1% error (1.8× improvement over a 22.0% roofline baseline), and a target-measured tier that adds one model-agnostic microbenchmark sweep to achieve 3.8% error. End-to-end median errors across six model families are reported as 15.4%, 12.8%, and 3.0% for TTFT, TPOT, and throughput in the cross-generation tier, and 14.3%, 6.2%, and 2.7% in the target-measured tier.

Significance. If the generalization of the learned efficiency term holds, KernelSight-LM would provide a valuable tool for evaluating LLM inference across diverse hardware with minimal target-specific data collection, supporting hardware/software co-design and capacity planning in production serving environments. The kernel-level bottleneck breakdowns are a particular strength for identifying optimization opportunities. The paper is credited for extending roofline models with a learned term and discrete-event simulation to capture serving dynamics, and for reporting concrete quantitative improvements over baselines.

major comments (3)
  1. [Abstract] The abstract claims a 12.1% per-kernel error for the cross-generation tier using 'no target-GPU measurements' and 'kernel microbenchmarks from previously profiled GPUs'. No information is given on the number of source GPU generations used to derive the learned efficiency term, the exact fitting procedure, or validation across multiple target generations. This is load-bearing for the central claim of 1.8× improvement over the roofline baseline, as the error may reflect tuning rather than portable generalization.
  2. [§3 (Model Description)] The decomposition into roofline kernel, communication, and host-overhead models with the learned efficiency term is described, but the manuscript does not clarify if the efficiency term is a single scalar or incorporates additional parameters, nor how it is fitted without target data. This directly affects whether the cross-generation predictions are independent of the target architecture.
  3. [§5 (Evaluation)] The end-to-end results (15.4% TTFT, 12.8% TPOT, 3.0% throughput for cross-generation) are presented across six model families, but the section supplies no experimental setup details, baseline implementations, validation splits, or confirmation that the learned term was not fitted in a manner that inflates the cross-generation performance. This undermines assessment of the reported errors.
minor comments (2)
  1. [Abstract] The specific model families used in the evaluation are not named; providing their identities would aid reproducibility and context.
  2. [Throughout] The notation and definitions for the learned efficiency term and its integration into the roofline model could be more explicitly introduced early in the text to improve accessibility.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the detailed and constructive feedback. The comments highlight areas where additional clarity on the cross-generation methodology and experimental setup would strengthen the manuscript. We address each major comment below and will incorporate revisions to provide the requested details without altering the core claims or results.

read point-by-point responses

  1. Referee: [Abstract] The abstract claims a 12.1% per-kernel error for the cross-generation tier using 'no target-GPU measurements' and 'kernel microbenchmarks from previously profiled GPUs'. No information is given on the number of source GPU generations used to derive the learned efficiency term, the exact fitting procedure, or validation across multiple target generations. This is load-bearing for the central claim of 1.8× improvement over the roofline baseline, as the error may reflect tuning rather than portable generalization.

    Authors: We agree the abstract would benefit from explicit mention of the source data scope to support the generalization claim. Section 3 of the manuscript details the use of microbenchmarks from multiple prior GPU generations to fit the efficiency term via regression, with validation on unseen target generations. We will revise the abstract to briefly note the source GPU generations and that fitting uses only prior data, preserving the reported 12.1% error and 1.8× improvement as measured on held-out targets. revision: yes

  2. Referee: [§3 (Model Description)] The decomposition into roofline kernel, communication, and host-overhead models with the learned efficiency term is described, but the manuscript does not clarify if the efficiency term is a single scalar or incorporates additional parameters, nor how it is fitted without target data. This directly affects whether the cross-generation predictions are independent of the target architecture.

    Authors: The efficiency term is implemented as a single scalar per kernel type, fitted exclusively on source GPU microbenchmarks by regressing the ratio of measured to roofline-predicted latency. No target-GPU data enters the fit, ensuring independence. We will add an explicit sentence in §3.2 stating the scalar nature and confirming the fitting procedure uses only prior-generation data. revision: yes

  3. Referee: [§5 (Evaluation)] The end-to-end results (15.4% TTFT, 12.8% TPOT, 3.0% throughput for cross-generation) are presented across six model families, but the section supplies no experimental setup details, baseline implementations, validation splits, or confirmation that the learned term was not fitted in a manner that inflates the cross-generation performance. This undermines assessment of the reported errors.

    Authors: We acknowledge that §5 would be strengthened by expanded setup details. The evaluation uses source-only fitting of the efficiency term with a validation split on unseen targets and generations; baselines are pure roofline models without the learned term. We will revise §5 to include the validation splits, baseline implementations, and explicit confirmation that fitting excludes all target data, ensuring the reported errors reflect true cross-generation performance. revision: yes

Circularity Check

0 steps flagged

No significant circularity; cross-generation prediction tests generalization of fitted efficiency term on unseen GPUs.

full rationale

The paper's core claim decomposes inference into a roofline model plus a learned efficiency term fitted exclusively on microbenchmarks from previously profiled GPUs, then applies the term (with only target hardware specifications) to predict latencies on entirely unseen GPU generations. This is a standard held-out generalization test rather than a self-definitional loop or a fitted parameter renamed as a prediction on the same data. No equations or self-citations are shown reducing the reported 12.1% error to the input microbenchmarks by construction; the baseline comparison (pure roofline) further isolates the contribution of the fitted term as an independent modeling choice. The derivation chain therefore remains self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The central claim depends on a learned efficiency term whose fitting procedure is not detailed and on the assumption that the three-component decomposition plus discrete-event scheduler captures all relevant LLM serving dynamics.

free parameters (1)
  • learned efficiency term
    Adjustment factor in the roofline kernel model; described as learned and required for the reported accuracy gains.
axioms (1)
  • domain assumption LLM inference execution can be decomposed into independent roofline kernel, communication, and host-overhead models whose composition via discrete-event scheduling reproduces end-to-end behavior.
    Invoked to justify the simulator architecture and the two prediction tiers.

pith-pipeline@v0.9.1-grok · 5926 in / 1426 out tokens · 60223 ms · 2026-06-30T00:44:48.400177+00:00 · methodology

discussion (0)

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