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arxiv: 2405.14430 · v4 · submitted 2024-05-23 · 💻 cs.CV · cs.AI· cs.PF

PipeFusion: Patch-level Pipeline Parallelism for Diffusion Transformers Inference

Jiarui Fang , Jinzhe Pan , Aoyu Li , Xibo Sun , Jiannan Wang This is my paper

Pith reviewed 2026-05-24 01:15 UTC · model grok-4.3

classification 💻 cs.CV cs.AIcs.PF
keywords diffusion transformerspipeline parallelismpatch partitioninginference optimizationmulti-GPUimage generationcommunication reduction
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The pith

PipeFusion partitions diffusion transformer images into patches and reuses one-step-old feature maps to cut communication costs during multi-GPU inference.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces PipeFusion to lower the latency of high-resolution image generation with diffusion transformers on multiple GPUs. It splits both the image into patches and the model layers across devices, then runs a patch-level pipeline that overlaps computation with reduced data movement. Because inputs change only gradually across diffusion steps, the method reuses feature maps computed one step earlier to supply context for the current step. This reuse lowers the volume of inter-GPU transfers relative to tensor parallelism, sequence parallelism, and DistriFusion while also spreading parameters to improve memory efficiency on large models. Experiments on eight L40 GPUs report faster runtimes for PixArt, Stable Diffusion 3, and Flux.1.

Core claim

PipeFusion achieves state-of-the-art inference speed for diffusion transformers by applying patch-level pipeline parallelism that reuses one-step stale feature maps, thereby reducing communication volume compared with prior parallelism schemes while distributing parameters for better memory use on large models.

What carries the argument

Patch-level pipeline parallelism that reuses one-step stale feature maps to supply context for the current pipeline step.

If this is right

  • Larger DiT models such as Flux.1 become practical on PCIe GPU clusters because parameters are distributed rather than replicated.
  • Communication volume drops below that of tensor, sequence, and DistriFusion baselines, directly lowering end-to-end latency.
  • Memory footprint per device shrinks, allowing higher-resolution generation or batch sizes on the same hardware.
  • The pipeline schedule can be applied to any DiT variant that exhibits gradual input change across denoising steps.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same reuse idea could be tested on video or 3D diffusion models where temporal or spatial coherence is even stronger.
  • If the similarity assumption weakens at very late denoising steps, a hybrid schedule that switches to fresh maps near the end might preserve quality while retaining most of the speedup.
  • Extending the patch pipeline to heterogeneous GPU clusters would require only adjustments to the communication pattern, not to the core reuse logic.

Load-bearing premise

High similarity between inputs from successive diffusion steps lets one-step-old feature maps supply adequate context without materially harming final image quality.

What would settle it

Run the same models with and without the stale-map reuse on the eight-GPU setup and compare both wall-clock time and standard image-quality metrics such as FID; a large quality drop would falsify the central claim.

Figures

Figures reproduced from arXiv: 2405.14430 by Aoyu Li, Jiannan Wang, Jiarui Fang, Jinzhe Pan, Xibo Sun.

Figure 1
Figure 1. Figure 1: Workflow of DiTs inference. Input Temporal Redundancy: Diffusion Model entails the iterative prediction of noise from the input image or video. Recent research has highlighted the concept of input temporal redundancy, 2 [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Comparison of DistriFusion with Sequence Parallelism methods (DeepSpeed-Ulysses and [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Above: partitioning strategy for Input and DiTs backbone network. Below: Workflow of [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: The fresh part of activations during diffusion timestep [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Latency on Pixart of various parallel approaches on two image generation tasks with the [PITH_FULL_IMAGE:figures/full_fig_p007_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Latency on SD3-medium of various parallel approaches on two image generation tasks [PITH_FULL_IMAGE:figures/full_fig_p007_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Latency on Flux.1-dev of various parallel approaches on three image generation tasks with [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Scalability Analysis of Three DiTs on 8×L40: Leftmost figures depict Pixart performance on 1024px, 2048px, and 4096px images. The second from the right shows SD3 performance on 1024px. The rightmost figure illustrates Flux.1-dev performance on 1024px. The speedup to 1 GPU baseline is labeled on the points of pipefusion curves. Stable Diffusion 3 [PITH_FULL_IMAGE:figures/full_fig_p008_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Comparison of GPU memory usage across different models and resolutions. [PITH_FULL_IMAGE:figures/full_fig_p009_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Above: Showcases for 1024px Generation Images of PipeFusion and DistriFusion using [PITH_FULL_IMAGE:figures/full_fig_p021_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Latency of PipeFusion (without warmup) for various patch numbers [PITH_FULL_IMAGE:figures/full_fig_p022_11.png] view at source ↗
read the original abstract

This paper presents PipeFusion, an innovative parallel methodology to tackle the high latency issues associated with generating high-resolution images using diffusion transformers (DiTs) models. PipeFusion partitions images into patches and the model layers across multiple GPUs. It employs a patch-level pipeline parallel strategy to orchestrate communication and computation efficiently. By capitalizing on the high similarity between inputs from successive diffusion steps, PipeFusion reuses one-step stale feature maps to provide context for the current pipeline step. This approach notably reduces communication costs compared to existing DiTs inference parallelism, including tensor parallel, sequence parallel and DistriFusion. PipeFusion enhances memory efficiency through parameter distribution across devices, ideal for large DiTs like Flux.1. Experimental results demonstrate that PipeFusion achieves state-of-the-art performance on 8$\times$L40 PCIe GPUs for Pixart, Stable-Diffusion 3, and Flux.1 models. Our source code is available at https://github.com/xdit-project/xDiT.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper proposes PipeFusion, a patch-level pipeline parallelism technique for Diffusion Transformer (DiT) inference. It partitions both image patches and model layers across GPUs and reuses one-step-stale feature maps (exploiting similarity between successive diffusion steps) to reduce inter-GPU communication relative to tensor parallelism, sequence parallelism, and DistriFusion. The method is evaluated on PixArt, Stable Diffusion 3, and Flux.1, claiming state-of-the-art latency on 8×L40 PCIe GPUs while preserving output quality; source code is released.

Significance. If the quality-preservation claim holds, PipeFusion would offer a practical route to lower-latency, memory-efficient inference for large DiTs on commodity multi-GPU hardware. The open-source release is a concrete strength that supports reproducibility and follow-on work.

major comments (2)
  1. [Experimental results / Evaluation] The central performance claim rests on the unverified assumption that one-step stale feature maps supply adequate context without materially degrading image quality. No ablation isolating the quality impact of this reuse (FID, CLIP score, or human preference with vs. without stale maps) is referenced in the evaluation description, which is load-bearing for the communication-savings argument.
  2. [Abstract and Experimental results] The abstract asserts SOTA latency on 8×L40 GPUs for PixArt, SD3, and Flux.1 yet supplies no quantitative numbers, baselines, or quality metrics. Without these data the SOTA claim cannot be assessed.
minor comments (1)
  1. Notation for patch partitioning and pipeline stages should be defined once with a consistent symbol table or figure.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback. We address the two major comments below and will incorporate revisions to strengthen the manuscript.

read point-by-point responses

  1. Referee: [Experimental results / Evaluation] The central performance claim rests on the unverified assumption that one-step stale feature maps supply adequate context without materially degrading image quality. No ablation isolating the quality impact of this reuse (FID, CLIP score, or human preference with vs. without stale maps) is referenced in the evaluation description, which is load-bearing for the communication-savings argument.

    Authors: We agree that an explicit ablation isolating the quality impact of one-step stale feature reuse would provide stronger evidence. The current manuscript reports overall quality metrics (FID, CLIP) for PipeFusion versus baselines but does not include a controlled with/without-stale comparison. We will add this ablation study in the revised version. revision: yes

  2. Referee: [Abstract and Experimental results] The abstract asserts SOTA latency on 8×L40 GPUs for PixArt, SD3, and Flux.1 yet supplies no quantitative numbers, baselines, or quality metrics. Without these data the SOTA claim cannot be assessed.

    Authors: We acknowledge that the abstract currently lacks specific numerical results. In the revision we will expand the abstract to include key latency figures, the compared baselines, and quality metrics that support the SOTA claim on 8×L40 GPUs. revision: yes

Circularity Check

0 steps flagged

No circularity: engineering method with external benchmarks and no self-referential derivations

full rationale

The paper describes a patch-level pipeline parallelism technique for DiT inference that reuses one-step stale feature maps based on observed input similarity across diffusion steps. This is presented as an empirical engineering choice, not a derived prediction or first-principles result. No equations, fitted parameters renamed as predictions, or self-citation chains appear in the load-bearing claims. Performance is benchmarked against external baselines (tensor parallel, sequence parallel, DistriFusion) on Pixart, SD3, and Flux.1, with code released for reproduction. The similarity assumption is stated explicitly but does not reduce any result to its own inputs by construction. This is a standard non-circular systems paper.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on the domain assumption of sufficient feature similarity across diffusion steps and standard assumptions about GPU interconnect costs; no free parameters or new entities are introduced in the abstract.

axioms (1)
  • domain assumption Inputs from successive diffusion steps have high similarity allowing reuse of one-step stale feature maps
    Invoked to justify reduced communication while preserving pipeline correctness.

pith-pipeline@v0.9.0 · 5711 in / 1178 out tokens · 31182 ms · 2026-05-24T01:15:25.711684+00:00 · methodology

discussion (0)

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Forward citations

Cited by 3 Pith papers

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    ChunkFlow achieves up to 1.28x step-time speedup and up to 49% lower peak GPU memory for DiT inference by using a first-order model to guide communication-aware chunked prefetching.

  2. CoCoDiff: Optimizing Collective Communications for Distributed Diffusion Transformer Inference Under Ulysses Sequence Parallelism

    cs.DC 2026-04 unverdicted novelty 6.0

    CoCoDiff achieves 3.6x average and 8.4x peak speedup for distributed DiT inference on up to 96 GPU tiles via tile-aware all-to-all, V-first scheduling, and selective V communication.

  3. GENSERVE: Efficient Co-Serving of Heterogeneous Diffusion Model Workloads

    cs.DC 2026-04 unverdicted novelty 6.0

    GENSERVE improves SLO attainment by up to 44% for co-serving heterogeneous T2I and T2V diffusion workloads via step-level preemption, elastic parallelism, and joint scheduling.

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