Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
As of 9 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 25 inbound Pith citation observations for arXiv:2506.14074.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-08T06:32:00.761636+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-06T00:45:24.830628Z
A source-named dated measurement, never combined with another source.
Source: arxiv_reference, observed 2026-07-04T15:09:55.523834Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation 4fefa38d-41cd-4acc-9549-bf39075cadd6 · inbound
Revolution or Hype? Seeking the Limits of Large Models in Hardware Design cites this paper.
Revolution or Hype? Seeking the Limits of Large Models in Hardware Design Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 14
- Resolution
- unresolved
- no resolver link, observed 2026-08-05T05:50:29.819033Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation b4554590-ea58-42ce-b493-aeecd25816e8 · inbound
HWE-Bench: Benchmarking LLM Agents on Real-World Hardware Bug Repair Tasks cites this paper.
HWE-Bench: Benchmarking LLM Agents on Real-World Hardware Bug Repair Tasks Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 21
- Resolution
- verified exact
- arxiv_id, observed 2026-05-10T11:30:18.925789Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation 6f2649cf-7615-4134-8db7-818d406a1eb7 · inbound
Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement cites this paper.
Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 29
- Resolution
- verified exact
- arxiv_id, observed 2026-05-10T10:49:56.192583Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation 05a66429-c6ca-49f4-a6b7-c14695a4b5dc · inbound
Spec2Cov: An Agentic Framework for Code Coverage Closure of Digital Hardware Designs cites this paper.
Spec2Cov: An Agentic Framework for Code Coverage Closure of Digital Hardware Designs Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 10
- Resolution
- verified exact
- arxiv_id, observed 2026-05-10T08:17:37.542242Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation 3d8b9413-7a79-4d95-a73a-12b631e29fea · inbound
Spec2Cov: An Agentic Framework for Code Coverage Closure of Digital Hardware Designs cites this paper.
Spec2Cov: An Agentic Framework for Code Coverage Closure of Digital Hardware Designs Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 10
- Resolution
- verified exact
- arxiv_id, observed 2026-05-22T10:21:24.133526Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation e9be5ce3-29dd-49ba-a076-528c46bea872 · inbound
Understanding Inference-Time Token Allocation and Coverage Limits in Agentic Hardware Verification cites this paper.
Understanding Inference-Time Token Allocation and Coverage Limits in Agentic Hardware Verification Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 27
- Resolution
- verified exact
- arxiv_id, observed 2026-05-10T08:02:25.037753Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation 66379d30-45c0-42e4-963b-2152a4175cc1 · inbound
ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration cites this paper.
ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 2
- Resolution
- verified exact
- arxiv_id, observed 2026-05-11T13:36:08.318679Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation c4b63f7b-e5d4-4c85-a536-402b82b2bc90 · inbound
SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation cites this paper.
SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 16
- Resolution
- verified exact
- arxiv_id, observed 2026-05-12T09:36:26.586732Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation e755e713-d726-41ca-9ac0-5d652deb0f22 · inbound
RuC: HDL-Agnostic Rule Completion Benchmark Generation cites this paper.
RuC: HDL-Agnostic Rule Completion Benchmark Generation Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 9
- Resolution
- verified exact
- arxiv_id, observed 2026-05-12T10:01:29.100776Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation 70ad44aa-d7cd-4b57-b824-2abbb68a642a · inbound
ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation cites this paper.
ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 20
- Resolution
- verified exact
- arxiv_id, observed 2026-06-30T22:05:05.892499Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation 98ed2132-5527-46c7-aa76-26bd1d1860bf · inbound
RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision cites this paper.
RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 15
- Resolution
- verified exact
- arxiv_id, observed 2026-05-19T14:42:37.291864Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation 1eca5840-96c5-4243-80c5-a90980d25c3c · inbound
AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications cites this paper.
AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 17
- Resolution
- verified exact
- arxiv_id, observed 2026-07-01T16:25:49.883285Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation 6731d922-2cd0-4f9f-a721-5779b433838a · inbound
CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs cites this paper.
CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 34
- Resolution
- verified exact
- arxiv_id, observed 2026-07-02T15:57:07.337550Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation ad382723-37ab-41e8-a3aa-e1d3cccd64ac · inbound
RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models cites this paper.
RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 29
- Resolution
- verified exact
- arxiv_id, observed 2026-07-03T00:47:30.492161Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation 2d10777a-2324-4932-a571-b82ca9fbc2ac · inbound
Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curation cites this paper.
Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curation Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 15
- Resolution
- verified exact
- arxiv_id, observed 2026-07-03T14:58:32.897580Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation 7449a3fe-d2c1-4234-9a82-afca4826b75a · inbound
Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement cites this paper.
Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 35
- Resolution
- verified exact
- arxiv_id, observed 2026-07-03T21:28:59.398936Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation 222552d4-52ea-4ec0-abce-269bc2e165ce · inbound
Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement cites this paper.
Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 35
- Resolution
- unresolved
- no resolver link, observed 2026-07-15T10:45:43.149976Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 90f9680b-adf9-41a8-8e44-a8343be03cc5 · inbound
CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research cites this paper.
CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 83
- Resolution
- verified exact
- arxiv_id, observed 2026-07-04T15:09:55.525727Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation d767d608-007f-4b11-897a-32f4e6770163 · inbound
CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research cites this paper.
CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 84
- Resolution
- verified exact
- arxiv_id, observed 2026-06-30T12:44:39.759592Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation 71f95b0d-fe5c-455d-bc95-6b9a60d62bd0 · inbound
CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research cites this paper.
CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 80
- Resolution
- unresolved
- no resolver link, observed 2026-08-02T10:03:40.395732Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 08b2b0cb-1415-4b92-9a54-412c598df5aa · inbound
Agentic Hardware Design as Repository-Level Code Evolution cites this paper.
Agentic Hardware Design as Repository-Level Code Evolution Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 4
- Resolution
- verified exact
- arxiv_id, observed 2026-07-01T18:45:58.335609Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation c54ee891-db8a-4e77-9d1d-edc26fd2d2d5 · inbound
ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation cites this paper.
ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 18
- Resolution
- unresolved
- no resolver link, observed 2026-08-02T07:12:17.834017Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation c960fe16-40d7-4547-8447-a1ef52a6030a · inbound
When LLMs Over-Answer: Measuring and Mitigating Quality Issues in LLM-Based Hardware Description Language Question Answering cites this paper.
When LLMs Over-Answer: Measuring and Mitigating Quality Issues in LLM-Based Hardware Description Language Question Answering Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 21
- Resolution
- unresolved
- no resolver link, observed 2026-08-01T19:12:13.427128Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 1c791175-4f57-49b6-a500-c8c73ff05263 · inbound
Can AI Agents Really Complete RTL-to-GDS? Lessons from Benchmarking Tool-Interactive EDA Workflows cites this paper.
Can AI Agents Really Complete RTL-to-GDS? Lessons from Benchmarking Tool-Interactive EDA Workflows Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 11
- Resolution
- unresolved
- no resolver link, observed 2026-08-01T17:46:04.086561Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 60de5fe6-2dfe-447c-b64e-78344d342b27 · inbound
FinHardBench: Can LLMs Generate Latency-Aware Hardware for Financial Computing? cites this paper.
FinHardBench: Can LLMs Generate Latency-Aware Hardware for Financial Computing? Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Reference 26
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T00:45:24.830628Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.