Paper Citation Record · LEDGER

UVLLM: An Automated Universal RTL Verification Framework using LLMs

As of 15 August 2026, this Paper Citation Record lists 46 of 46 outbound references and 12 inbound Pith citation observations for arXiv:2411.16238.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2411.16238 v1

Coverage vector

measured 46 of 46 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-12T13:27:04.926059Z

measured 58 of 58 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-14T06:32:32.682623+00:00

measured 12 of 12 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-07T13:20:54.004393Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-07-03T03:37:35.786682Z

Reference resolution

46 of 46 outbound references displayed

verified exact0
verified fuzzy26
unresolved20
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation d9344ccb-72e7-4dc7-84f9-6910d42d1844 · outbound

This paper cites Are we there yet? a study on the state of high-level synthesis,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Are we there yet? a study on the state of high-level synthesis,

Reference 1

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.751536Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation dacba6d7-d158-4b0e-94d9-0cc30697fe1a · outbound

This paper cites A survey of test based automatic program repair.

UVLLM: An Automated Universal RTL Verification Framework using LLMs A survey of test based automatic program repair

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.495145Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 1df5bd7f-1172-4af6-b207-bb119a491436 · outbound

This paper cites A critical review on the evaluation of automated program repair systems,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs A critical review on the evaluation of automated program repair systems,

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.482272Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation c07183d9-4940-42c7-8e63-b4b81388507c · outbound

This paper cites A Critical Review of Large Language Model on Software Engineering: An Example from ChatGPT and Automated Program Repair.

UVLLM: An Automated Universal RTL Verification Framework using LLMs A Critical Review of Large Language Model on Software Engineering: An Example from ChatGPT and Automated Program Repair

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.763906Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ece1c15d-b72a-4e31-8d2c-fa9dbcb8f444 · outbound

This paper cites Thinkrepair: Self- directed automated program repair,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Thinkrepair: Self- directed automated program repair,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.466859Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation b2d792f0-f9ef-43a8-86f9-b4924b73731e · outbound

This paper cites Automated c/c++ program repair for high-level synthesis via large language models,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Automated c/c++ program repair for high-level synthesis via large language models,

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.452513Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation fdf287f9-4ef7-4942-a2cb-93a7297a4141 · outbound

This paper cites Cirfix: automatically repairing defects in hardware design code,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Cirfix: automatically repairing defects in hardware design code,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.440654Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 16d120d2-5e58-4267-adb2-eebd796ad531 · outbound

This paper cites Strider: Signal value transition-guided defect repair for hdl programming assignments,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Strider: Signal value transition-guided defect repair for hdl programming assignments,

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.426180Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 8dcec1d1-12a7-4282-a1ba-c9f0d8b454b8 · outbound

This paper cites Rtl- repair: Fast symbolic repair of hardware design code,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Rtl- repair: Fast symbolic repair of hardware design code,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.410543Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation b15d9b46-f34e-46d3-9b98-4c08eedcc847 · outbound

This paper cites Verilogeval: Evaluating large language models for verilog code generation,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Verilogeval: Evaluating large language models for verilog code generation,

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.788860Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c7438387-f811-450c-aceb-2221d9541330 · outbound

This paper cites VeriGen: A Large Language Model for Verilog Code Generation.

UVLLM: An Automated Universal RTL Verification Framework using LLMs VeriGen: A Large Language Model for Verilog Code Generation

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.792249Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f976c84e-befc-4313-99c1-402343c457ae · outbound

This paper cites Chip-Chat: Challenges and Opportunities in Conversational Hardware Design.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Chip-Chat: Challenges and Opportunities in Conversational Hardware Design

Reference 12

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.796193Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d1dcbdf0-a3c6-4be9-b4f9-5214ac786f34 · outbound

This paper cites Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.800026Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a35e97b2-b227-45f4-9410-4dbc401856be · outbound

This paper cites ChipNeMo: Domain-Adapted LLMs for Chip Design.

UVLLM: An Automated Universal RTL Verification Framework using LLMs ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 14

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.804481Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation fd3dcde3-e1c2-4f75-8011-6cc6cd82d753 · outbound

This paper cites RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models.

UVLLM: An Automated Universal RTL Verification Framework using LLMs RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.809499Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation be5f8335-179d-4e48-a2f5-a4b2003d951f · outbound

This paper cites HDLdebugger: Streamlining HDL debugging with Large Language Models.

UVLLM: An Automated Universal RTL Verification Framework using LLMs HDLdebugger: Streamlining HDL debugging with Large Language Models

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.813397Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 678ce00d-68d8-40d4-873c-96e4aa62ba67 · outbound

This paper cites MEIC: Re-thinking RTL Debug Automation using LLMs.

UVLLM: An Automated Universal RTL Verification Framework using LLMs MEIC: Re-thinking RTL Debug Automation using LLMs

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.818201Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 95766525-8b5d-4cdd-b6bb-ac9084df2299 · outbound

This paper cites Llm4sechw: Leveraging domain-specific large language model for hardware debug- ging,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Llm4sechw: Leveraging domain-specific large language model for hardware debug- ging,

Reference 18

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.821818Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ba191429-b2aa-4032-b335-5e1b3ad26898 · outbound

This paper cites A Prompt Pattern Catalog to Enhance Prompt Engineering with ChatGPT.

UVLLM: An Automated Universal RTL Verification Framework using LLMs A Prompt Pattern Catalog to Enhance Prompt Engineering with ChatGPT

Reference 19

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.825408Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 4ba35ae9-4a54-48e7-acbf-bb0cc0dc2379 · outbound

This paper cites A Systematic Survey of Prompt Engineering in Large Language Models: Techniques and Applications.

UVLLM: An Automated Universal RTL Verification Framework using LLMs A Systematic Survey of Prompt Engineering in Large Language Models: Techniques and Applications

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.829405Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0bf95ec1-678a-4111-bbd9-99be77991698 · outbound

This paper cites Chain-of-thought prompting elicits reasoning in large language models,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Chain-of-thought prompting elicits reasoning in large language models,

Reference 21

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.833013Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 93727b8f-c84e-4bad-a79d-c3831ec3ddc8 · outbound

This paper cites GPT-4 pricing for OpenAI API,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs GPT-4 pricing for OpenAI API,

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.374170Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 0710ab38-b893-4b92-9b6b-30d03d082797 · outbound

This paper cites Robust functional verification framework based in uvm applied to an aes encryption module,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Robust functional verification framework based in uvm applied to an aes encryption module,

Reference 23

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.361253Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation a4885599-5eeb-448f-951d-550790691b05 · outbound

This paper cites Spear, SystemVerilog for Verification: A Guide to Learning the Testbench Language Features.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Spear, SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.347180Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation be16c5e9-7d0e-4c32-bc4f-815f07a63fd4 · outbound

This paper cites Methodology for hardware/software co- verification in c/c++ (short paper),.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Methodology for hardware/software co- verification in c/c++ (short paper),

Reference 25

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.334586Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 58e1ab95-827c-4da1-a26f-220e24e17559 · outbound

This paper cites A fast hardware/software co-verification method for system-on-a-chip by using a c/c++ simulator and fpga emulator with shared register communication,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs A fast hardware/software co-verification method for system-on-a-chip by using a c/c++ simulator and fpga emulator with shared register communication,

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.320891Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation eb6d5e87-740e-4594-a894-4a5f3715651f · outbound

This paper cites Generative ai assertions in uvm-based system verilog functional verifi- cation,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Generative ai assertions in uvm-based system verilog functional verifi- cation,

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.308601Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation b4d55ff0-4415-4ada-90f0-d5faed07f279 · outbound

This paper cites Towards mitigating llm hallucination via self reflection,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Towards mitigating llm hallucination via self reflection,

Reference 28

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.856541Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b2d1bca7-7c3a-4ea9-a70e-2d1b40fe7264 · outbound

This paper cites Measuring and mitigating hallucinations in large lan- guage models: amultifaceted approach,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Measuring and mitigating hallucinations in large lan- guage models: amultifaceted approach,

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.288666Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 677c6a19-97b4-43ac-b359-35ef36ca24aa · outbound

This paper cites Truth-o-meter: Collaborating with llm in fighting its hallucinations,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Truth-o-meter: Collaborating with llm in fighting its hallucinations,

Reference 30

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.274247Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation d5ef96dc-fb71-4608-9a92-bb0c7478d15d · outbound

This paper cites Hallucination detection: Robustly discerning reliable answers in large language models,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Hallucination detection: Robustly discerning reliable answers in large language models,

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.261937Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation ae345c14-8821-4b13-a0bf-d7de5fc5c27f · outbound

This paper cites Survey of hallucination in natural language generation,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Survey of hallucination in natural language generation,

Reference 32

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.870497Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation dfdd742d-ca39-40df-9c0e-0efc58e7605d · outbound

This paper cites RewardBench: Evaluating Reward Models for Language Modeling.

UVLLM: An Automated Universal RTL Verification Framework using LLMs RewardBench: Evaluating Reward Models for Language Modeling

Reference 33

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.874221Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 235386da-c85f-44d1-8ef6-e63e613a1525 · outbound

This paper cites Structured outputs - OpenAI API,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Structured outputs - OpenAI API,

Reference 34

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.242812Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation f7821d98-337b-4840-baa8-02cea94b10c1 · outbound

This paper cites Understanding bug fix patterns in verilog,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Understanding bug fix patterns in verilog,

Reference 35

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.231524Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 4f003e40-066d-4b49-bc4e-fa9296439c90 · outbound

This paper cites Debugging in the brave new world of reconfigurable hardware,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Debugging in the brave new world of reconfigurable hardware,

Reference 36

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.219330Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation b6349b8e-391c-4ed6-9ecf-51064f89e6de · outbound

This paper cites Evaluating code complexity triggers, use of complexity measures and the influence of code complex- ity on maintenance time,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Evaluating code complexity triggers, use of complexity measures and the influence of code complex- ity on maintenance time,

Reference 37

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.207252Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation dae15a0d-97fa-4c82-9daf-218d30c363e4 · outbound

This paper cites RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model.

UVLLM: An Automated Universal RTL Verification Framework using LLMs RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 38

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.894147Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d3255d0a-44fa-4e41-9d76-fd5a70222588 · outbound

This paper cites VCS: Synopsys Verification Continuum,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs VCS: Synopsys Verification Continuum,

Reference 39

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.193940Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 7aee5f5e-b6cd-4b3d-b442-8032d42063c9 · outbound

This paper cites Icarus Verilog,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Icarus Verilog,

Reference 40

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.181141Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation d0e55953-8801-48a0-a55e-fdaa32377bf4 · outbound

This paper cites ModelSim,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs ModelSim,

Reference 41

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.167962Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 074ed55e-2489-44e3-a81c-a4bc26f6c062 · outbound

This paper cites Yosys Open SYnthesis Suite,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Yosys Open SYnthesis Suite,

Reference 42

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.155244Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 4fec4b8e-bc0d-4c0f-8549-032a45c81077 · outbound

This paper cites Verilator,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Verilator,

Reference 43

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.141860Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation bd9dfccf-a1e6-4f52-a87c-cff9ee9e3b7b · outbound

This paper cites Evaluating Large Language Models Trained on Code.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Evaluating Large Language Models Trained on Code

Reference 44

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.917969Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 5f57fb60-f0e2-447d-829c-a43df1b0ccbd · outbound

This paper cites Llm- based test-driven interactive code generation: User study and empirical evaluation,.

UVLLM: An Automated Universal RTL Verification Framework using LLMs Llm- based test-driven interactive code generation: User study and empirical evaluation,

Reference 45

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T13:27:05.127986Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation e459b95b-7251-4f59-ba29-55a4cf35f2f1 · outbound

This paper cites DebugBench: Evaluating Debugging Capability of Large Language Models.

UVLLM: An Automated Universal RTL Verification Framework using LLMs DebugBench: Evaluating Debugging Capability of Large Language Models

Reference 46

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.926059Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Pith citing papers

Observation e1be1a23-3e27-4bd0-bec1-2e349456e72e · inbound

From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification cites this paper.

From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification UVLLM: An Automated Universal RTL Verification Framework using LLMs

Reference 36

Resolution: verified exact; arxiv_id, observed 2026-05-22T18:01:54.457392Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 4814d0dd-40e7-4b4c-aaaf-bd95d274d4c9 · inbound

iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs cites this paper.

iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs UVLLM: An Automated Universal RTL Verification Framework using LLMs

Reference 52

Resolution: unresolved; no resolver link, observed 2026-08-07T13:20:54.004393Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 83eb66be-b52e-4e20-8616-ddb0962692af · inbound

A Large Language Model-based Multi-Agent Framework for Analog Circuits' Sizing Relationships Extraction cites this paper.

A Large Language Model-based Multi-Agent Framework for Analog Circuits' Sizing Relationships Extraction UVLLM: An Automated Universal RTL Verification Framework using LLMs

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-06T23:21:48.744820Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation eff81140-5be2-4877-8353-85d0ab0285c8 · inbound

SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models cites this paper.

SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models UVLLM: An Automated Universal RTL Verification Framework using LLMs

Reference 70

Resolution: unresolved; no resolver link, observed 2026-08-06T22:55:09.342893Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 8bcb6235-43a2-43c1-b374-b420266b22d5 · inbound

ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs cites this paper.

ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs UVLLM: An Automated Universal RTL Verification Framework using LLMs

Reference 15

Resolution: verified exact; arxiv_id, observed 2026-05-13T19:08:10.056094Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 3cf5a0fd-3ebe-418b-b70a-87447c63a544 · inbound

Automated SVA Generation with LLMs cites this paper.

Automated SVA Generation with LLMs UVLLM: An Automated Universal RTL Verification Framework using LLMs

Reference 26

Resolution: verified exact; arxiv_id, observed 2026-05-11T09:06:00.672550Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 9280a143-df73-4280-bd94-acad8c511d3f · inbound

Spec2Cov: An Agentic Framework for Code Coverage Closure of Digital Hardware Designs cites this paper.

Spec2Cov: An Agentic Framework for Code Coverage Closure of Digital Hardware Designs UVLLM: An Automated Universal RTL Verification Framework using LLMs

Reference 16

Resolution: verified exact; arxiv_id, observed 2026-05-10T08:17:37.539666Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 979e7fce-df0d-4d71-88e5-e92145bbb92a · inbound

Spec2Cov: An Agentic Framework for Code Coverage Closure of Digital Hardware Designs cites this paper.

Spec2Cov: An Agentic Framework for Code Coverage Closure of Digital Hardware Designs UVLLM: An Automated Universal RTL Verification Framework using LLMs

Reference 16

Resolution: verified exact; arxiv_id, observed 2026-05-22T10:21:24.145915Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation d0b85209-8d14-4707-bc55-2dd67e0b2027 · inbound

Understanding Inference-Time Token Allocation and Coverage Limits in Agentic Hardware Verification cites this paper.

Understanding Inference-Time Token Allocation and Coverage Limits in Agentic Hardware Verification UVLLM: An Automated Universal RTL Verification Framework using LLMs

Reference 13

Resolution: verified exact; arxiv_id, observed 2026-05-10T08:02:25.025032Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation ba8976de-96b2-479b-8c32-850d71fcc1de · inbound

Clover: A Neural-Symbolic Agentic Harness with Stochastic Tree-of-Thoughts for Verified RTL Repair cites this paper.

Clover: A Neural-Symbolic Agentic Harness with Stochastic Tree-of-Thoughts for Verified RTL Repair UVLLM: An Automated Universal RTL Verification Framework using LLMs

Reference 9

Resolution: malformed identifier; arxiv_id, observed 2026-05-10T06:11:20.107384Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 61c11091-8a90-41d2-8c17-1c7b14bfc099 · inbound

UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification cites this paper.

UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification UVLLM: An Automated Universal RTL Verification Framework using LLMs

Reference 21

Resolution: verified exact; arxiv_id, observed 2026-05-11T18:31:13.625813Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 99a51729-d332-40d1-b13f-45684cf34b68 · inbound

LongRTL: Graph-Similarity-Guided LLM-driven Long Context RTL Optimization cites this paper.

LongRTL: Graph-Similarity-Guided LLM-driven Long Context RTL Optimization UVLLM: An Automated Universal RTL Verification Framework using LLMs

Reference 6

Resolution: verified exact; arxiv_id, observed 2026-07-03T03:37:35.788154Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.